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hc05 MC68HC05BS8D/h mc68hc05bs8 mc68hc705bs8 technical data !motorola mc68hc05bs8 !motorola technical data

1 2 3 4 5 6 7 8 9 10 11 12 13 14 a tpg 1 general description pin description input/output ports memory and registers resets and interrupts timers pulse width modulation m-bus serial interface sync signal processor cpu core and instruction set low power modes operating modes electrical specifications mechanical specifications mc68hc705bs8
1 2 3 4 5 6 7 8 9 10 11 12 13 14 a general description pin description input/output ports memory and registers resets and interrupts timers pulse width modulation m-bus serial interface sync signal processor cpu core and instruction set low power modes operating modes electrical specifications mechanical specifications mc68hc705bs8 tpg 2
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tpg 4 conventions register and bit mnemonics are de?ed in the paragraphs describing them. an overbar is used to designate an active-low signal, eg: reset . unless otherwise stated, blank cells in a register diagram indicate that the bit is either unused or reserved; shaded cells indicate that the bit is not described in the following paragraphs; ? is used to indicate an unde?ed state (on reset).
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mc68hc05bs8 motorola i paragraph number page number title table of contents 1 general description 1.1 features.................................................................................................................1-1 2 pin description 2.1 pin descriptions.....................................................................................................2-1 2.2 pin assignment......................................................................................................2-2 3 input/output ports 3.1 input/output programming ....................................................................................3-1 3.2 port a, b, and c.....................................................................................................3-2 3.3 pb7 - rspwm counter reset...............................................................................3-2 3.4 pc0:5 - keyboard interrupts ..................................................................................3-2 3.5 pc6 and pc7 - software supported m-bus sda and scl ...................................3-3 4 memory and registers 4.1 registers ...............................................................................................................4-1 4.2 ram.......................................................................................................................4-1 4.3 rom (mc68hc05bs8) .........................................................................................4-1 4.4 eprom (mc68hc705bs8)...................................................................................4-1 4.5 eeprom ...............................................................................................................4-2 4.5.1 eeprom control register...............................................................................4-2 4.5.2 eeprom options register..............................................................................4-3 4.5.3 read procedure...............................................................................................4-3 4.5.4 erase procedure ..............................................................................................4-4 4.5.5 programming procedure ..................................................................................4-4 tpg 7
motorola ii mc68hc05bs8 paragraph number page number title 5 resets and interrupts 5.1 resets ................................................................................................................5-1 5.1.1 power-on reset (por) ...................................................................................5-1 5.1.2 reset pin.......................................................................................................5-2 5.1.3 low voltage reset (lvr) .................................................................................5-2 5.1.4 computer operating properly (cop) reset ....................................................5-3 5.2 interrupts........................................................................................................5-3 5.2.1 non-maskable software interrupt (swi) ..........................................................5-5 5.2.2 maskable hardware interrupts.........................................................................5-5 5.2.2.1 external interrupt (irq )..............................................................................5-5 5.2.2.2 sync signal processor interrupt.................................................................5-7 5.2.2.3 m-bus interrupts.........................................................................................5-7 5.2.2.4 timer interrupts..........................................................................................5-8 5.2.2.5 core timer interrupts .................................................................................5-9 5.2.2.6 keyboard interrupt......................................................................................5-10 6 timers 6.1 programmable timer....................................................................................6-1 6.1.1 counter ............................................................................................................6-3 6.1.2 output compare register................................................................................6-4 6.1.3 input capture registers...................................................................................6-4 6.1.4 timer control register.....................................................................................6-5 6.1.5 timer status register (tsr) ...........................................................................6-6 6.1.6 programmable timer timing diagrams ...........................................................6-7 6.2 core timer ........................................................................................................6-10 6.2.1 ctimer counter register.................................................................................6-10 6.2.2 ctimer control and status register................................................................6-10 6.2.3 cop watchdog reset......................................................................................6-12 7 pulse width modulation 7.1 general purpose pulse width modulator ..............................................................7-1 7.1.1 general purpose pulse width modulator register (gpwm) ...........................7-2 7.2 raster positioning pulse width modulator ............................................................7-2 7.2.1 raster positioning pulse width modulator register (rspwm) .......................7-4 tpg 8
mc68hc05bs8 motorola iii paragraph number page number title 8 m-bus serial interface 8.1 m-bus interface features ......................................................................................8-1 8.2 m-bus protocol ......................................................................................................8-2 8.2.1 start signal...................................................................................................8-3 8.2.2 slave address transmission ............................................................................8-3 8.2.3 data transfer....................................................................................................8-4 8.2.4 repeated start signal ..................................................................................8-4 8.2.5 stop signal ....................................................................................................8-4 8.2.6 arbitration procedure .......................................................................................8-4 8.2.7 clock synchronization .....................................................................................8-5 8.2.8 handshaking ....................................................................................................8-5 8.3 m-bus registers ....................................................................................................8-6 8.3.1 m-bus address register (madr) ....................................................................8-6 8.3.2 m-bus frequency register (mfdr).................................................................8-6 8.3.3 m-bus control register (mcr) ........................................................................8-7 8.3.4 m-bus status register (msr)..........................................................................8-8 8.3.5 m-bus data i/o register (mdr) ......................................................................8-9 8.4 programming considerations ................................................................................8-11 8.4.1 initialization ......................................................................................................8-11 8.4.2 generation of a start signal and the first byte of data transfer..................8-11 8.4.3 software responses after transmission or reception of a byte .....................8-11 8.4.4 generation of the stop signal........................................................................8-12 8.4.5 generation of a repeated start signal ........................................................8-13 8.4.6 slave mode ......................................................................................................8-13 8.4.7 arbitration lost .................................................................................................8-13 8.5 software supported m-bus interface.....................................................................8-14 9 sync signal processor 9.1 introduction ............................................................................................................9-1 9.2 polarity correction .................................................................................................9-2 9.2.1 separate vertical sync input............................................................................9-2 9.2.2 separate horizontal or composite sync input .................................................9-2 9.3 sync detection ......................................................................................................9-3 9.4 free-running pseudo sync signal generator........................................................9-3 9.5 sync separation ....................................................................................................9-4 9.6 vertical sync pulse reshaper ...............................................................................9-5 9.7 sync signal counters ............................................................................................9-5 9.8 vsync interrupt....................................................................................................9-6 9.9 sampling pulse output ..........................................................................................9-7 9.10 ssp registers .......................................................................................................9-7 9.10.1 sync signal control and status register (sscsr) .........................................9-7 tpg 9
motorola iv mc68hc05bs8 paragraph number page number title 9.10.2 vertical frequency register (vfr) ..................................................................9-9 9.10.3 line frequency registers (lfrs) ....................................................................9-9 9.10.4 interrupt line count register (ilcr) ...............................................................9-10 9.10.5 sampling pulse register (spr).......................................................................9-10 9.11 system operation..................................................................................................9-10 10 cpu core and instruction set 10.1 registers .............................................................................................................10-1 10.1.1 accumulator (a) .............................................................................................10-1 10.1.2 index register (x) ...........................................................................................10-2 10.1.3 program counter (pc)....................................................................................10-2 10.1.4 stack pointer (sp)..........................................................................................10-2 10.1.5 condition code register (ccr).......................................................................10-2 10.2 instruction set ......................................................................................................10-3 10.2.1 register/memory instructions ........................................................................10-4 10.2.2 branch instructions ........................................................................................10-4 10.2.3 bit manipulation instructions ..........................................................................10-4 10.2.4 read/modify/write instructions.......................................................................10-4 10.2.5 control instructions ........................................................................................10-4 10.2.6 tables.............................................................................................................10-4 10.3 addressing modes...............................................................................................10-11 10.3.1 inherent..........................................................................................................10-11 10.3.2 immediate ......................................................................................................10-11 10.3.3 direct .............................................................................................................10-11 10.3.4 extended........................................................................................................10-12 10.3.5 indexed, no offset ..........................................................................................10-12 10.3.6 indexed, 8-bit offset .......................................................................................10-12 10.3.7 indexed, 16-bit offset .....................................................................................10-12 10.3.8 relative ..........................................................................................................10-13 10.3.9 bit set/clear ....................................................................................................10-13 10.3.10 bit test and branch.........................................................................................10-13 11 low power modes 11.1 stop mode.........................................................................................................11-1 11.2 wait mode..........................................................................................................11-1 11.3 data retention mode ..........................................................................................11-3 11.4 cop watchdog timer considerations.................................................................11-3 tpg 10
mc68hc05bs8 motorola v paragraph number page number title 12 operating modes 12.1 user mode (normal operation) ...........................................................................12-2 12.2 self-check mode .................................................................................................12-2 12.3 bootstrap mode ...................................................................................................12-4 13 electrical specifications 13.1 maximum ratings ................................................................................................13-1 13.2 thermal characteristics.......................................................................................13-1 13.3 dc electrical characteristics ...............................................................................13-2 13.4 control timing .....................................................................................................13-3 13.5 pulse width modulator timing .............................................................................13-4 13.6 m-bus timing.......................................................................................................13-5 13.7 sync signal processor timing .............................................................................13-6 14 mechanical specifications 14.1 44-pin qfp package............................................................................................14-2 a mc68hc705bs8 a.1 features................................................................................................................ a-1 a.2 memory map......................................................................................................... a-1 a.3 modes of operation .............................................................................................. a-3 a.3.1 user mode ...................................................................................................... a-3 a.3.2 bootstrap mode............................................................................................... a-3 a.4 eprom programming .......................................................................................... a-3 a.4.1 program control register (pcr) .................................................................... a-4 a.4.2 eprom programming sequence ................................................................... a-4 a.5 pin assignments ................................................................................................... a-5 a.6 electrical speci?ations........................................................................................ a-5 a.6.1 maximum ratings ........................................................................................... a-5 tpg 11
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mc68hc05bs8 motorola vii figure number page number title list of figures 1-1 mc68hc05bs8/mc68hc705bs8 block diagram .................................................1-2 2-1 pin assignment for 44-pin qfp package ...............................................................2-2 3-1 port i/o circuitry .....................................................................................................3-2 4-1 memory map ..........................................................................................................4-5 5-1 power-on reset and reset timing......................................................................5-2 5-2 interrupt stacking order .........................................................................................5-4 5-3 external interrupt circuit and timing ......................................................................5-6 6-1 programmable timer block diagram......................................................................6-2 6-2 timer state timing diagram for reset ...................................................................6-8 6-3 timer state timing diagram for input capture .......................................................6-8 6-4 timer state timing diagram for output compare ..................................................6-9 6-5 timer state diagram for timer over?w ................................................................6-9 6-6 core timer block diagram .....................................................................................6-11 7-1 gpwm timing example .........................................................................................7-1 7-2 gpwm output con?uration..................................................................................7-2 7-3 rspwm timing example .......................................................................................7-3 7-4 rspwm block diagram..........................................................................................7-3 8-1 m-bus interface block diagram ..............................................................................8-2 8-2 m-bus transmission signal diagram ......................................................................8-3 8-3 clock synchronization ............................................................................................8-5 8-4 flowchart of m-bus interrupt routine.....................................................................8-10 8-5 software supported m-bus interrupt......................................................................8-14 9-1 sync signal polarity correction ..............................................................................9-3 9-2 sync separator.......................................................................................................9-4 9-3 vttl pulse widths for different input signal formats ..........................................9-5 9-4 vertical frequency counter timing ........................................................................9-6 9-5 example of ssp operation .....................................................................................9-11 10-1 programming model .............................................................................................10-1 10-2 stacking order ......................................................................................................10-2 11-1 stop and wait flowchart...................................................................................11-2 12-1 flowchart of mode entering .................................................................................12-1 12-2 self-check mode timing ......................................................................................12-2 12-3 mc68hc05bs8 self-test circuit..........................................................................12-3 tpg 13
motorola viii mc68hc05bs8 figure number page number title 13-1 pwm timing ......................................................................................................... 13-4 13-2 m-bus timing ....................................................................................................... 13-5 14-1 44-pin qfp package (case no. 824a-01)............................................................ 14-2 a-1 mc68hc705bs8 memory map..............................................................................a-2 a-2 pin assignments for 44-pin qfp package..............................................................a-5 tpg 14
mc68hc05bs8 motorola ix ta b l e number page number title list of tables 3-1 i/o pin functions ....................................................................................................3-1 4-1 erase mode select .................................................................................................4-2 4-2 register outline......................................................................................................4-6 5-1 reset/interrupt vector addresses ..........................................................................5-4 6-1 cop reset and rti rates .....................................................................................6-12 8-1 m-bus prescaler .....................................................................................................8-6 9-1 vertical frame frequencies ....................................................................................9-9 10-1 mul instruction.....................................................................................................10-5 10-2 register/memory instructions...............................................................................10-5 10-3 branch instructions ...............................................................................................10-6 10-4 bit manipulation instructions.................................................................................10-6 10-5 read/modify/write instructions .............................................................................10-7 10-6 control instructions...............................................................................................10-7 10-7 instruction set .......................................................................................................10-8 10-8 m68hc05 opcode map.........................................................................................10-10 12-1 mode selection.....................................................................................................12-2 12-2 self-check report ................................................................................................12-4 13-1 dc electrical characteristics for mc68hc05bs8 ................................................13-2 13-2 control timing ......................................................................................................13-3 13-3 m-bus interface input signal timing.....................................................................13-5 13-4 m-bus interface output signal timing..................................................................13-5 13-5 sync signal processor timing..............................................................................13-6 a-1 mc68hc705bs8 operating mode entry conditions............................................. a-3 tpg 15
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mc68hc05bs8 motorola 1-1 general description 1 1 general description the mc68hc05bs8 hcmos microcontroller is a member of the mc68hc05 family of low-cost single-chip microcontrollers. it is particularly suitable as a multi-sync computer monitor controller. this 8-bit microcontroller unit (mcu) contains on-chip oscillator, cpu, ram, rom, eeprom, i/o, timers, cop watchdog, m-bus serial interface system, pwm, and sync signal processor. the mc68hc705bs8 is an eprom version of the mc68hc05bs8. all references to the mc68hc05bs8 apply equally to the mc68hc705bs8, unless otherwise stated. references speci? to the mc68hc705bs8 are italicized in the text, and also, for quick reference, they are summarized in appendix a. 1.1 features fully static chip design featuring the industry standard 8-bit m68hc05 core power saving stop and wait modes 256 bytes of ram (64 bytes for stack) 10k-bytes of rom for mc68hc05bs8 10k-bytes of eprom for mc68hc705bs8 512 bytes of eeprom 24 bidirectional i/o lines 6 keyboard interrupts core timer with rti and cop watchdog reset 2 m-bus (i 2 c ? ) serial interfaces (one full h/w, one s/w with hardware support) single channel 6-bit general purpose pwm single channel 7-bit raster positioning pwm 16-bit programmable timer with one tcap and one tcmp sync signal processor tpg 17 ? i 2 c-bus is a proprietary philips interface bus
motorola 1-2 mc68hc05bs8 general description 1 low voltage reset (lvr) available in 44-pin qfp package figure 1-1 mc68hc05bs8/ mc68hc705bs8 block diagram user rom/ eprom - 10k bytes self-check/ bootstrap rom - 512 bytes ram - 256 bytes accumulator index register stack pointer program counter condition code register m68hc05 cpu reset irq 0 12 1 1h i nzc osc power osc1 osc2 vdd vss ddr a port a pa0 - pa7 pc0 pc1 pc2 pc3 pc4 pc5 pc6/scl2 pc7/sda2 8 ? 2 m-bus interrupt 1 1 7 0 7 50 1 0 0 0 0 0 0 4 15 0 7 ddr b port b pb0 - pb7 port c charge pump 8 ddr c keyboard interrupt eeprom - 512 bytes lvr m-bus interface sync signal processor general purpose pwm raster positioning pwm 16-bit timer core timer cop watchdog reset gpwm rsa rsb rclk sda scl hsync csync httl vttl sam vsync tcap tcmp circuit tpg 18
mc68hc05bs8 motorola 2-1 pin description 2 2 pin description this section provides a description of the functional pins of the mc68hc05bs8 microcontroller. 2.1 pin descriptions pin name 44-pin qfp pin no. description vdd, vss 38, 39 power is supplied to the mcu using these pins. vdd is the positive power supply; vss is ground. irq / vpp 34 in the user mode this pin is the external hardware interrupt i rq . two choices of interrupt triggering sensitivity are available through the option register: 1) negative-edge sensitive triggering, or 2) negative-level sensitive triggering. in bootstrap mode on the mc68hc705bs8, this is the eprom programming voltage input pin. reset 35 the active low reset input is not required for start-up, but can be used to reset the mcu internal state and provide an orderly software start-up procedure. osc1, osc2 36, 37 these pins provide connections to the on-chip oscillator. the oscillator can be driven by an at-crystal circuit or a ceramic resonator with a maximum frequency of 4.4mhz. osc1 may also be driven by an external oscillator if an external crystal/resonator circuit is not used. example showing crystal connections. pa0-pa7 33-26 these eight i/o lines comprise port a. the state of any pin is software programmable. all port a lines are con?ured as input during power-on or external reset. 2m w 36pf 4.2mhz 36pf osc1 osc2 mcu tpg 19
motorola 2-2 mc68hc05bs8 pin description 2 2.2 pin assignment pb0-pb7 25-18 these eight i/o lines comprise port b. the state of any pin is software programmable. all port b lines are con?ured as input during power-on or external reset. pb7 is also used as the rspwm counter reset input when pb7 is set as an input pin and the counter reset enable bit is set in the gpwm register (bit 6 of $0010). pc0-pc7 17-10 these eight i/o lines comprise port c. the state of any pin is software programmable. all port c lines are con?ured as input during power-on or external reset. pc0-pc5 become keyboard interrupt input pins when the corresponding bits are set in the keyboard interrupt register ($001e). pc6 and pc7 are sda and scl respectively, when used for the software supported m-bus interface. sda, scl 2, 3 these are the hardware m-bus interface data and clock lines. tcap 9 this input pin controls the input capture function of the 16-bit free-running timer. tcmp 8 this output pin indicates when a timer compare is successful. gpwm 7 this is the output pin of the general purpose pwm. rsa, rsb 5, 6 these are the two excursive outputs of the raster positioning pwm rclk 4 this is the input clock to drive the rspwm counter. hsync, vsync 40, 41 these two input pins are for the video sync signals from the host computer. csync 42 this is the composite sync signal input from the host computer. sam 43 this is the output of an sample signal from the sync signal processor. httl, vttl 44, 1 these are the output from the hsync and vsync inputs or the signals separated from csync input. figure 2-1 pin assignment for 44-pin qfp package pin name 44-pin qfp pin no. description irq reset osc2 12 13 15 16 17 18 19 20 21 22 14 33 32 30 29 28 27 26 25 24 23 31 pa0 pa1 pa3 pa4 pa5 pa6 pa7 pb0 pb1 pb2 pa2 vttl sda rclk rsa rsb gpwm tcmp tcap pc7 pc6 scl pc5 pc4 pc2 pc1 pc0 pb7 pb5 pb4 pb3 pc3 httl sam vsync hsync vss vdd osc1 csync 1 2 4 5 6 7 8 9 10 11 3 pb6 44 43 41 40 39 38 36 35 34 42 37 tpg 20
mc68hc05bs8 motorola 3-1 input/output ports 3 3 input/output ports the mc68hc05bs8 has 24 i/o lines, arranged as three 8-bit ports (port a, b, and c). each i/o line is individually programmable as either input or output, under the software control of the data direction registers. port c also shares with keyboard interrupt and the software supported m-bus functions. to avoid glitches on the output pins, data should be written to the i/o port data register before writing ?? to the corresponding data direction register bits to set the pins to output mode. 3.1 input/output programming bidirectional port lines may be programmed as an input or an output under software control. the direction of the pins is determined by the state of the corresponding bit in the port data direction register (ddr). each port has an associated ddr. any i/o port pin is con?ured as an output if its corresponding ddr bit is set to a logic one. a pin is con?ured as an input if its corresponding ddr bit is cleared to a logic zero. at power-on or reset, all ddrs are cleared, con?uring all port pins as inputs. the data direction registers are capable of being written to or read by the mcu. during the programmed output state, a read of the data register actually reads the value of the output data latch and not the i/o pin. the operation of the standard port hardware is shown schematically in figure 3-1. this is summarized in table 3-1 which shows the effect of reading from or writing to an i/o pin in various circumstances. table 3-1 i/o pin functions r/w ddr i/o pin function 0 0 the i/o pin is in input mode. data is written into the output data latch. 0 1 data is written into the output data latch and output to the i/o pin. 1 0 the state of the i/o pin is read. 1 1 the i/o pin is in an output mode. the output data latch is read. note: r/w is an internal signal. tpg 21
motorola 3-2 mc68hc05bs8 input/output ports 3 3.2 port a, b, and c these are standard m68hc05 bidirectional i/o ports, each comprising a data register and a data direction register. all three are 8-bit ports. reset does not affect the state of the data registers, but clears the data direction registers, thereby returning all port pins to input mode. writing a ? to any ddr sets the corresponding port pin to output mode. 3.3 pb7 - rspwm counter reset in addition to normal i/o function, pb7 can be software selectable to input a reset signal to the raster positioning pulse width modulator counter. the reset pulse requires an active high signal. 3.4 pc0:5 - keyboard interrupts six keyboard interrupt inputs are available on port pins pc0 to pc5. each pin is enabled for keyboard interrupt by setting the corresponding keyboard interrupt enable bit in the kbi register (bits 0 to 5 of $001e). when the kbi bit is set, the corresponding port c pin will be con?ured as an input pin, regardless of the ddrc setting, an internal pull-up resistor is connected to the pin. figure 3-1 port i/o circuitry input register bit input i/o output i/o pin data direction register bit latched output data bit internal mc68hc05 connections tpg 22
mc68hc05bs8 motorola 3-3 input/output ports 3 the interrupt signal is latched, and it should be cleared by writing a ? to the kbic bit in the kbi register (bit 6 of $001e) in the interrupt service routine. this should be cleared after the key is debounced, otherwise unwanted keyboard interrupt signals may be generated. the keyboard interrupt is negative-edge sensitive only, and the interrupt service routine is speci?d by the contents of the memory locations $3ff0 and $3ff1. kbic - keyboard interrupt clear 1 (set) clear keyboard interrupt latch. kbe5:0 - keyboard interrupt enable 5:0 1 (set) enable keyboard interrupt for the corresponding bit. 0 (clear) disable keyboard interrupt for the corresponding bit. 3.5 pc6 and pc7 - software supported m-bus sda and scl pc6 and pc7 are used for sda and sdl respectively when con?ured for the software supported m-bus interface. this m-bus interface is operated by software emulation, with hardware interrupt circuit connected to pc6 and pc7. address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset kbi register $001e kbic kbe5 kbe4 kbe3 kbe2 kbe1 kbe0 0000 0000 tpg 23
motorola 3-4 mc68hc05bs8 input/output ports 3 this page left blank intentionally tpg 24
mc68hc05bs8 motorola 4-1 memory and registers 4 4 memory and registers the mc68hc05bs8/ mc68hc705bs8 has a 16k-byte memory map consisting of i/o registers, user rom/ eprom , user ram, eeprom, self-check/ bootstrap rom as shown in figure 4-1. 4.1 registers all the i/o, control and status registers of the mc68hc05bs8 are located within the ?st 64-byte block of the memory map (address $0000 to $003f). 4.2 ram the user ram consists of 256 bytes of memory, from $0040 to $013f. this is shared with a 64 byte stack area. the stack begins at $00ff and counts down to $00c0. note: using the stack area for data storage or temporary work locations requires care to prevent the data from being overwritten due to stacking from an interrupt or subroutine call. 4.3 rom (mc68hc05bs8) the user rom consists of 10k-bytes of memory, from $1800 to $3fdf. 4.4 eprom (mc68hc705bs8) the user eprom consists of 10k-bytes of memory, from $1800 to $3fdf. tpg 25
motorola 4-2 mc68hc05bs8 memory and registers 4 4.5 eeprom the eeprom consists of 512 bytes, from $0200 to $03ff. a charge pump is built on the chip for the operation of eeprom. programming and erasing are controlled by writing to the eeprom control register at address $0007. 4.5.1 eeprom control register eeosc - eeprom charge pump oscillator enable 1 (set) internal oscillator turned on to clock the eeprom charge pump. it requires a time t rcon to stabilize. (min. 1 m s). 0 (clear) internal oscillator turned off. eeprom charge pump clocked by internal bus clock. eer1, eer0 - eeprom erase mode select bits these two bits select one of the three erase modes. refer to table 4-1 below. the eeprom memory space is divided into two 256 byte blocks. block 1 is located at address $0200-$02ff, and block 2 is located at $0300-$03ff. providing the eelat and eepgm bits are ?? the eer1 and eer0 bits indicate whether the access to the eeprom is for an erase or programming purpose. block protect function applies on block 2 of the eeprom memory space. eelat - eeprom programming latch control 1 (set) eeprom address and data bus con?ured for programming (writes to eeprom cause address and data to be latched). eeprom is in programming mode and cannot be read when this bit is set. 0 (clear) eeprom address and data bus con?ured for normal reads. eer1, eer0, and eepgm are forced to ??. address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset eepcr $0007 eeosc eer1 eer0 eelat eepgm 0000 0000 table 4-1 erase mode select eer1 eer0 erase mode 0 0 no erase 0 1 byte erase 1 0 block erase (block 1 or block 2) 1 1 bulk erase (block 1 and block 2) tpg 26
mc68hc05bs8 motorola 4-3 memory and registers 4 eepgm - eeprom programming power enable 1 (set) programming power switched on to eeprom array. if eelat 1 1 then eepgm cannot be set. 0 (clear) programming power switched off to eeprom array. 4.5.2 eeprom options register eeprt - eeprom protect 1 (set) block 2 ($300-$3ff) con?ured for read/write. 0 (clear) block 2 ($300-$3ff) con?ured for read only. when this bit is erased to ?? writing to block 2 is not possible until the next external or power-on reset occurs. lvr - low voltage reset 1 (set) low voltage reset function is disabled. 0 (clear) low voltage reset function is enabled. this bit does not control any eeprom operation, but enables/disables the lvr function. when enabled, and the mcu will reset if v dd drops below v lv r . when this bit is changed, its new value will have no effect until next external power-on reset. 4.5.3 read procedure to read data from eeprom, the eelat bit must be cleared. eepgm, eer1, and eer0 bits will be forced to zero. eeprom is read as if it were normal rom. the v pp charge pump generator is off since eepgm is zero. if a read is performed while elat is set, data will be read as $ff. address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset eeopr $0200 eeprt lvr unaffected tpg 27
motorola 4-4 mc68hc05bs8 memory and registers 4 4.5.4 erase procedure there are three types of erase operation mode (see table 4-1): byte erase, block erase, and bulk erase. 1) to perform byte erase operation, set eelat=1, eer1=0, and eer0=1, write any data to the address to be erase, and set eepgm for a time t ebyte . 2) to perform block erase operation, set eelat=1, eer1=1, and eer0=0, write any data to any address in the block, and set eepgm for a time t eblock . 3) to perform bulk erase operation, set eelat=1, eer1=1, and eer0=0, write any data to any address in the eeprom map, and set eepgm for a time t ebulk . note: erase operation to any part of block 2 is not possible if the eeprt bit is programmed to ?? 4.5.5 programming procedure to program the content of eeprom, set eelat bits, write data to the desired address, and set the eepgm bit. after the required programming delay t prog , eelat must be cleared, which also resets eepgm. during a programming operation, any access to the eeprom will return $ff. to program a second byte, eelat must be cleared before it is set, or the programming will have no effect. tpg 28
mc68hc05bs8 motorola 4-5 memory and registers 4 figure 4-1 memory map self-check/ bootstrap 512 bytes program port a data register $00 $0000 i/o 64 bytes self-check/ bootstrap 16 bytes user vectors 16 bytes vectors port b data register $01 port c data register $02 not used $03 port a data direction register $04 port b data direction register $05 port c data direction register $06 eeprom register $07 core timer control and status register $08 core timer register $09 sync signal control and status register $0a vfreq register $0b $0c $0d $0e $0f $10 $11 timer control register $12 timer status register $13 input capture high register $14 input capture low register $15 output compare high register $16 output compare low register $17 counter high register $18 counter low register $19 alternate counter high register $1a alternate counter low register $1b eprom programming control register $1c option register $1d keyboard interrupt register $1e line frequency high register line frequency low register interrupt line count register sampling pulse register general purpose pulse width modulator register raster positioning pulse width modulator register not used (192) eeprom 512 bytes not used (4.25k) user rom/ eprom 10k-bytes $003f $0040 $00c0 $00ff $013f $0200 $03ff $1600 $17ff $3fdf $3fe0 $3fef $3ff0 $3fff $1800 keyboard $3ff0 m-bus $3ff2 ctimer $3ff4 timer $3ff6 vsync $3ff8 irq $3ffa swi $3ffc reset $3ffe not used $20 not used $38 $3f not used not used $3e not used $3d m-bus data register $3c m-bus status register $3b m-bus control register $3a m-bus frequency divider register $39 m-bus address register user ram 256 bytes stack 64 bytes $1f not used $0200 eeprom options register tpg 29
motorola 4-6 mc68hc05bs8 memory and registers 4 table 4-2 register outline register name address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset port a data $0000 pa7 pa6 pa5 pa4 pa3 pa2 pa1 pa0 unaffected port b data $0001 pb7 pb6 pb5 pb4 pb3 pb2 pb1 pb0 unaffected port c data $0002 pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 unaffected not used $0003 port a data direction $0004 ddra7 ddra6 ddra5 ddra4 ddra3 ddra2 ddra1 ddra0 0000 0000 port b data direction $0005 ddrb7 ddrb6 ddrb5 ddrb4 ddrb3 ddrb2 ddrb1 ddrb0 0000 0000 port c data direction $0006 ddrc7 ddrc6 ddrc5 ddrc4 ddrc3 ddrc2 ddrc1 ddrc0 0000 0000 eeprom control $0007 eeosc eer1 eer0 eelat eepgm 0000 0000 core timer control and status $0008 ctof rtif ctofe rtie rt1 rt0 0000 0011 core timer $0009 ct7 ct6 ct5 ct4 ct3 ct2 ct1 ct0 0000 0000 sync signal control and status $000a vpol hpol vdet hdet sout insrt sin1 sin0 0000 0000 vfreq $000b vf7 vf6 vf5 vf4 vf3 vf2 vf1 vf0 0000 0000 line frequency high $000c vf8 lf11 lf10 lf9 lf8 0000 0000 line frequency low $000d lf7 lf6 lf5 lf4 lf3 lf2 lf1 lf0 0000 0000 interrupt line counter $000e vsie lc6 lc5 lc4 lc3 lc2 lc1 lc0 0000 0010 sampling pulse $000f sp6 sp5 sp4 sp3 sp2 sp1 sp0 0000 0010 general pwm $0010 ode cre gpw5 gpw4 gpw3 gpw2 gpw1 gpw0 0000 0000 raster positioning pwm $0011 rsp rspw6 rspw5 rspw4 rspw3 rspw2 rspw1 rspw0 0000 0000 timer control $0012 icie ocie toie iedg olvl 0000 00u1 timer status $0013 icf ocf tof uuu0 0000 input capture high $0014 ic15 ic14 ic13 ic12 ic11 ic10 ic9 ic8 unaffected input capture low $0015 ic7 ic6 ic5 ic4 ic3 ic2 ic1 ic0 unaffected output compare high $0016 oc15 oc14 oc13 oc12 oc11 oc10 oc9 oc8 unaffected output compare low $0017 oc7 oc6 oc5 oc4 oc3 oc2 oc1 oc0 unaffected counter high $0018 tc15 tc14 tc13 tc12 tc11 tc10 tc9 tc8 $ff counter low $0019 tc7 tc6 tc5 tc4 tc3 tc2 tc1 tc0 $fc alternate counter high $001a ac15 ac14 ac13 ac12 ac11 ac10 ac9 ac8 $ff alternate counter low $001b ac7 ac6 ca5 ac4 ac3 ac2 ac1 ac0 $fc eprom programming control $001c reserved elat pgm 0000 0000 option $001d into cop 0100 0000 keyboard interrupt $001e kbic kbe5 kbe4 kbe3 kbe2 kbe1 kbe0 0000 0000 not used $001f tpg 30
mc68hc05bs8 motorola 4-7 memory and registers 4 not used $0020 to $0038 m-bus address $0039 mad7 mad6 mad5 mad4 mad3 mad2 mad1 0000 000- m-bus frequency divider $003a fd4 fd3 fd2 fd1 fd0 0000 0000 m-bus control $003b men mien msta mtx txak sifc siic 0000 0000 m-bus status $003c mcf mass mbb mal sif srw mif rxak 1000 0001 m-bus data $003d md7 md6 md5 md4 md3 md2 md1 md0 unde?ed not used $003e not used $003f eeprom options $0200 eeprt lvr unaffected table 4-2 register outline register name address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset tpg 31
motorola 4-8 mc68hc05bs8 memory and registers 4 this page left blank intentionally tpg 32
mc68hc05bs8 motorola 5-1 resets and interrupts 5 5 resets and interrupts the section describes the reset and interrupt functions available on the mc68hc05bs8. 5.1 resets the mc68hc05bs8 can be reset in four ways: by the initial power-on reset function, (por) by an active low input to the reset pin, (reset ) by a cop watchdog timer reset, (copr) and by a low voltage reset, (lvr) any of these resets will cause the program to go to its starting address, speci?d by the contents of memory locations $3ffe and $3fff, and cause the interrupt mask (i-bit) of the condition code register to be set. 5.1.1 power-on reset (por) the power-on reset occurs when a positive transition is detected on the supply voltage, v dd . the power-on reset is used strictly for power-up conditions, and should not be used to detect any drops in the power supply voltage. there is no provision for a power-down reset. the power-on circuitry provides for a 4064 t cyc delay from the time that the oscillator becomes active. if the external reset pin is low at the end of the 4064 t cyc time out, the processor remains in the reset condition until reset goes high. the user must ensure that v dd has risen to a point where the mcu can operate properly prior to the time the 4064 por cycles have elapsed. if there is doubt, the external reset pin should remain low until such time that v dd has risen to the minimum operating voltage speci?d. tpg 33
motorola 5-2 mc68hc05bs8 resets and interrupts 5 5.1.2 reset pin the reset input pin is used to reset the mcu to provide an orderly software start-up procedure. when using the external reset, the reset pin must stay low for a minimum of 1.5t cyc . the reset pin contains an internal schmitt trigger as part of its input to improve noise immunity. 5.1.3 low voltage reset (lvr) when the lvr function is enabled, an internal reset is generated if v dd drops below v lv r . (see section 13 for value of v lv r .) this lvr reset function is enabled/disabled by programming or erasing bit 0 in the eeprom options register ($0200). refer to section 4.5.2. figure 5-1 power-on reset and reset timing vdd osc2 pin 1 internal clock 2 internal address bus 2 internal data bus 2 reset 3ffe 3fff new pc 3ffe 3ffe 3fff t vddr vdd threshold (typically 1-2v) 4064 t cyc t oxov t cyc 3 new pch new pcl op code t rl =1.5t cyc pch pcl op code new pc notes: 1. osc2 is not meant to represent frequency. it is only used to represent time. 2. internal clock, internal address bus, and internal data bus signals are not available externally. 3. next rising edge of internal clock after rising edge of reset initiates reset sequence. tpg 34
mc68hc05bs8 motorola 5-3 resets and interrupts 5 5.1.4 computer operating properly (cop) reset the mc68hc05bs8 contains a watchdog timer that automatically times out if this timer is not reset (cleared) within a speci? amount of time by a program reset sequence. note: cop time-out is prevented by periodically writing a ? to bit 0 of address $3ff0. if the watchdog timer is allowed to time-out, an internal reset is generated to reset the mcu. because the internal reset signal is used, the mcu comes out of a cop reset in the same operating mode as it was in when the cop time-out was generated. the cop reset function is enabled after a reset, and it can be disabled by writing a ? to bit 6 in the option register at address $001d. once disabled, it cannot be enabled except by a reset function. see section 6.2.3 for more information on the cop watchdog timer. 5.2 interrupts the mc68hc05bs8 can be interrupted by different sources ?six maskable hardware interrupt and one non-maskable software interrupt: software interrupt instruction (swi) external signal on the irq pin sync signal processor (ssp) programmable timer (timer) core timer (ctimer) m-bus interface (mbus) keyboard (kbi) if the interrupt mask bit (i-bit) of the ccr is set, all maskable interrupts (internal and external) are disabled. clearing the i-bit enables interrupts. interrupts cause the processor to save the register contents on the stack and to set the interrupt mask (i-bit) to prevent additional interrupts. the rti instruction causes the register contents to be recovered from the stack and normal processing to resume. unlike reset, hardware interrupts do not cause the current instruction execution to be halted, but are considered pending until the current instruction is complete. the current instruction is the one already fetched and being operated on. when the current instruction is complete, the processor checks all pending hardware interrupts. if interrupts are not masked (ccr i-bit clear) the processor proceeds with interrupt processing; otherwise, the next instruction is fetched and executed. table 5-1 shows the relative priority of all the possible interrupt sources. tpg 35
motorola 5-4 mc68hc05bs8 resets and interrupts 5 figure 5-2 interrupt stacking order table 5-1 reset/interrupt vector addresses register flag name interrupt cpu interrupt vector address priority reset reset $3ffe-$3fff software swi $3ffc-$3ffd external interrupt irq $3ffa-$3ffb sscr vsync ssp $3ff8-$3ff9 tsr tof timer over?w timer $3ff6-$3ff7 ocf output compare icf input capture ctcsr ctof core timer over?w ctimer $3ff4-$3ff5 rtif core timer interrupt msr mif m-bus mbus $3ff2-$3ff3 sif keyboard kbi $3ff0-$3ff1 condition code register accumulator index register program counter (high byte) program counter (low byte) $00c0 (bottom of stack) $00c1 $00c2 $00fd $00fe $00ff (top of stack) unstacking 1 2 3 4 5 5 4 3 2 1 stacking order order highest lowest tpg 36
mc68hc05bs8 motorola 5-5 resets and interrupts 5 5.2.1 non-maskable software interrupt (swi) the software interrupt (swi) is an executable instruction and a non-maskable interrupt: it is execute regardless of the state of the i-bit in the ccr. if the i-bit is zero (interrupt enabled), swi is executed after interrupts that were pending when the swi was fetched, but before interrupts generated after the swi was fetched. the swi interrupt service routine address is speci?d by the contents of memory locations $3ffc and $3ffd. 5.2.2 maskable hardware interrupts if the interrupt mask bit (i-bit) of the ccr is set, all maskable interrupts (internal and external) are masked. clearing the i-bit allows interrupt processing to occur. note: the internal interrupt latch is cleared in the ?st part of the interrupt service routine; therefore, one external interrupt pulse could be latched and serviced as soon as the i-bit is cleared. 5.2.2.1 external interrupt (irq ) the external interrupt irq can be software con?ured for ?egative-edge or ?egative-level sensitive triggering by the into bit in the option register. into 1 (set) negative-edge sensitive triggering for irq . 0 (clear) negative-level sensitive triggering for irq . when the signal of the external interrupt pin, irq , satis?s the condition selected, an external interrupt occurs. the actual processor interrupt is generated only if the interrupt mask bit of the condition code register is also cleared. when the interrupt is recognized, the current state of the processor is pushed onto the stack and the interrupt mask bit in the condition code register is set. this masks further interrupts until the present one is serviced. the service routine address is speci?d by the contents $3ffa & $3ffb. the interrupt logic recognizes negative edge transitions and pulses (special case of negative edges) on the external interrupt line. figure 5-3 shows both a block diagram and timing for the interrupt line (irq ) to the processor. the ?st method is used if pulses on the interrupt line are spaced far enough apart to be serviced. the minimum time between pulses is equal to the number of cycles required to execute the interrupt service routine plus 21 cycles. once a pulse occurs, the address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset option register $001d into cop 01-- ---- tpg 37
motorola 5-6 mc68hc05bs8 resets and interrupts 5 figure 5-3 external interrupt circuit and timing irq t ilih t ilil edge sensitive trigger condition the minimum pulse width t ilih is one internal bus period. the period t ilil should not be less than the number of t cyc cycles it takes to execute the interrupt service routine plus 21 tcyc cycles. t ilil wired ored interrupt signals irq if after servicing an interrupt the irq pin remains low, then the next interrupt is recognized. normally used with pull-up resistors for wired-or connection. (b) interrupt mode diagram level sensitive trigger condition + & external request interrupt power-on reset external reset external interrupt being serviced d c r q q v dd irq pin i-bit (ccr) (a) interrupt function diagram & + into bit (read of vectors) & tpg 38
mc68hc05bs8 motorola 5-7 resets and interrupts 5 next pulse should not occur until the mcu software has exited the routine (an rti occurs). the second con?uration shows several interrupt lines wired-or to perform the interrupt at the processor. thus, if the interrupt lines remain low after servicing one interrupt, the next interrupt is recognized. note: the internal interrupt latch is cleared in the ?st part of the service routine; therefore, one (and only one) external interrupt pulse could be latched during t ilil and serviced as soon as the i-bit is cleared. 5.2.2.2 sync signal processor interrupt the cpu will process an sync signal processor vsync interrupt if the following conditions are satis?d: 1) the i-bit of the ccr is cleared, 2) the vsie bit of the interrupt line count register (ilcr) is set, and 3) the value of the horizontal line counter matches the value set in the ilcr. this interrupt will vector to the interrupt service routine located at the address speci?d by the contents of $3ff8 and $3ff9. the vsync interrupt latch will be cleared automatically by fetching of these vectors. refer to section 9 for detailed description of sync signal processor. 5.2.2.3 m-bus interrupts the hardware m-bus interrupt is enabled when the m-bus interrupt enable bit (mien) of m-bus control register is set, provided the interrupt mask bit of the condition code register is cleared. the interrupt service routine address is speci?d by the contents of memory location $3ff2 and $3ff3. mif - m-bus interrupt 1 (set) an m-bus interrupt has occurred. 0 (clear) an m-bus interrupt has not occurred. when this bit is set, an interrupt is generated to the cpu if mien is set. this bit is set when one of the following events occurs: 1) completion of one byte of data transfer. it is set at the falling edge of the 9th clock - mcf set. address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset m-bus status register $001a mcf maas mbb mal sif srw mif rxak 1000 0001 tpg 39
motorola 5-8 mc68hc05bs8 resets and interrupts 5 2) a match of the calling address with its own speci? address in slave mode - maas set. 3) a loss of bus arbitration - mal set. this bit must be cleared by software in the interrupt routine. mcf - data transfer complete 1 (set) a byte transfer has been completed. 0 (clear) a byte is being transfer. maas - addressed as slave 1 (set) currently addressed as a slave. 0 (clear) not currently addressed. then cpu needs to check the srw bit and set its mtx bit accordingly. writing to the m-bus control register clears this bit. mal - arbitration lost 1 (set) lost arbitration in master mode. 0 (clear) no arbitration lost. sif - software m-bus interrupt 1 (set) signals on pc6 and pc7 pins satisfy the ?tart condition for the ?oft m-bus protocol. this bit cannot be set if the siic bit in the mcr is cleared. an interrupt to the cpu is generated only if the i-bit in the ccr is also cleared. 0 (clear) no ?oft m-bus interrupt. refer to section 8 for detailed description of m-bus interface. 5.2.2.4 timer interrupts there are three interrupt sources from the 16-bit free-running counter timer. address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset timer status register $0013 icf ocf tof uuu0 0000 tpg 40
mc68hc05bs8 motorola 5-9 resets and interrupts 5 icf - input capture flag this bit is set when a proper edge has been sensed by the input capture edge detector. it is cleared by reading the tsr (with icf set) followed by accessing the input capture register lsb ($0015). ocf - output compare flag this bit is set when the output compare register matches the counter register. it is cleared by reading the tsr (with ocf set) and then accessing the output compare register lsb ($0017). tof - timer over?w flag this bit is set during the counter transition from $ffff to $0000. it is cleared by reading the tsr (with tof set) followed by reading the counter lsb ($0019). all three timer interrupt ?gs have corresponding enable bits (icie, ocie, and toie) found in the timer control register (tcr) at location $12. reset clears all enable bits preventing an interrupt from occurring. the actual processor interrupt is generated only if the interrupt mask bit of the condition code register is also cleared. when the interrupt is recognized, the current state of the machine is pushed onto the stack and the interrupt mask bit in the condition code register is set. this masks further interrupts until the present one is serviced. the service routine address is speci?d by the contents of $fff6 and $fff7. refer to section 6.1 for detailed description of the 16-bit counter timer. 5.2.2.5 core timer interrupts there are two interrupt sources, tof and rtif bits of multi-function timer control and status register. the interrupt service routine address is speci?d by the contents of memory location $3ff4 and $3ff5. ctof - timer over?w 1 (set) ctimer counter over?w has occurred. 0 (clear) no ctimer counter over?w has occurred. this bit is set when the 8-bit ripple counter over?ws from $ff to $00; a timer over?w interrupt will occur, if ctofe is set. ctof is cleared by writing a ? to the bit. address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset ctimer control and status register $0008 ctof rtif ctofe rtie rt1 rt0 0000 0011 tpg 41
motorola 5-10 mc68hc05bs8 resets and interrupts 5 rtif - real time interrupt flag 1 (set) a real time interrupt has occurred. 0 (clear) a real time interrupt has not occurred. refer to section 6.2 for detailed description of the ctimer. 5.2.2.6 keyboard interrupt keyboard interrupt functions are available on pc0-pc5. each port pin can be individually con?ured for the keyboard interrupt function in the kbi register at $0010. once con?ured, an interrupt is recognized by a high to low transition (negative edge) sensed on the pin and the i-bit in the ccr is also cleared. the interrupt service routine is speci?d by the contents of the memory locations $3ff0 and $3ff1. tpg 42
mc68hc05bs8 motorola 6-1 timers 6 6 timers 6.1 programmable timer the timer consists of a 16-bit free-running counter driven by a ?ed divide-by-four prescaler. this timer can be used for many purposes, including input waveform measurements while simultaneously generating an output waveform. pulse widths can vary from several microseconds to many seconds. figure 6-1 shows a block diagram for the programmable timer. because the timer has a 16-bit architecture, the i/o registers for the input capture and output compare functions are pairs of 8-bit registers (high byte and low byte). generally, assessing the low byte of a speci? timer function allows full control of that function. however, an access of the high byte inhibits that speci? timer function until the low byte is also accessed. note: the i-bit in the condition code register should be set while manipulating both the high and low byte register of a speci? timer function to ensure that an interrupt does not occur. ten 8-bit registers are associated with the programmable timer. timer control register (tcr) $12 timer status register (tsr) $13 input capture register high byte - $14, low byte - $15 output compare register high byte - $16, low byte - $17 counter register high byte - $18, low byte - $19 alternate counter register high byte - $1a, low byte - $1b a description of each register is provided in the following paragraphs. tpg 43
motorola 6-2 mc68hc05bs8 timers 6 figure 6-1 programmable timer block diagram mc68hc05bs8 internal bus output compare register 16 bit free running counter alternate counter register 8 bit buffer input capture register output compare circuit overflow detect circuit edge detect register ? 4 icie ocie toie iedg olvl icf ocf tof interrupt circuit d c r q internal processor clock timer control reg. ($12) output level register edge input output level timer status reg. ($13) reset $16 $17 $18 $19 $1a $1b $14 $15 tcap tcmp tpg 44
mc68hc05bs8 motorola 6-3 timers 6 6.1.1 counter counter register location high byte - $18, low byte - $19 alternate counter register high byte - $1a, low byte - $1b the key element in the programmable timer is a 16-bit, free-running counter or counter register, preceded by a prescaler that divides the internal processor clock by four. the prescaler gives the timer a resolution of 0.95 m s if the internal bus clock is 4.2mhz. the counter is incremented during the low portion of the internal bus clock. software can read the counter at any time without affecting its value. the double-byte, free-running counter can be read from either of two locations, $18 and $19 (counter register) or $1a and $1b (counter alternate register). reading only the least signi?ant byte (lsb) of the free-running counter ($19 or $1b) receives the count value at the time of the read. if the most signi?ant byte (msb) ($18 or $1a) is read ?st, the lsb ($19 or $1b) is transferred to a buffer. this buffer value remains ?ed after the ?st msb read, even if the msb is read several times. this buffer is accessed when the lsb ($19 or $1b) is read, and thus, completes a read sequence of the complete counter value. reading the timer counter register low byte after reading the timer status register clears the timer over?w ?g (tof), but reading the counter alternate register does not affect tof. therefore, the counter alternate register can be read any time without risk of missing timer over?w interrupts due to a cleared tof. the free-running counter is preset to $fffc during reset and is always a read-only register. during a power-on reset, the counter is also preset to $fffc and begins running after the oscillator start-up delay. the value in the free-running counter repeats every 262144 internal bus clock cycles. tof is set when the counter over?ws (from $ffff to $0000); this will cause an interrupt if toie (bit 5 of tcr) is set. in some timing control applications it may be desirable to reset the counter under software control. when the low byte of the counter ($19 or $1b) is written to, the counter is set to its reset value of $fffc. the divide-by-4 prescaler is also reset and the counter resumes normal counting operation. all of the ?gs and enable bits remain unaltered by this operation. if access has previously been made to the high byte of the free-running counter ($18 or $1a), then the reset counter operation terminates the access sequence. tpg 45
motorola 6-4 mc68hc05bs8 timers 6 6.1.2 output compare register the 16-bit output compare register is used for several purposes, such as indicating when a period of time has elapsed. all bits are readable and writable and are not affected by the timer hardware or reset. if the compare function is not needed, the output compare register can be used as storage locations. the contents of the output compare register are continually compared with the contents of the free-running counter and, if a match is found, the output compare ?g (ocf) in the timer status register is set. the output compare register value should be changed after each successful comparison to establish a new elapsed time-out. an interrupt can also accompany a successful output compare provided the interrupt enable bit (ocie) is set. (the free-running counter is updated every four internal bus clock cycles.) after a processor write cycle to the output compare register containing the msb ($16), the output compare function is inhibited until the lsb ($17) is also written. the user must write both bytes (locations) if the msb is written ?st. a write made only to the lsb ($17) will not inhibit the compare function. the processor can write to either byte of an output compare register without affecting the other byte. the minimum time required to update the output compare register is a function of the program rather than the internal hardware. because the output compare ?g and output compare register are not de?ed at power on, and not affected by reset, care must be taken when initializing output compare functions with software. the following procedure is recommended: 1) write to output compare register high-byte to inhibit further compares; 2) read the timer status register to initialize clearing of ocf; 3) write to output compare register low-byte to enable the output compare function. 6.1.3 input capture registers ?nput capture is a technique whereby an external signal (connected to tcap pin) is used to trigger a read of the free-running counter. in this way it is possible to relate the timing of an external signal to the internal counter value, and hence to elapsed time. address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset ocmph $0016 oc15 oc14 oc13 oc12 oc11 oc10 oc9 oc8 unaffected ocmpl $0017 oc7 oc6 oc5 oc4 oc3 oc2 oc1 oc0 unaffected address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset icaph $0014 ic15 ic14 ic13 ic12 ic11 ic10 ic9 ic8 unaffected icapl $0015 ic7 ic6 ic5 ic4 ic3 ic2 ic1 ic0 unaffected tpg 46
mc68hc05bs8 motorola 6-5 timers 6 the two 8-bit registers that make up the 16-bit input capture register, are read-only, and are used to latch the value of the free-running counter after the corresponding input capture edge detector senses a valid transition. the level transition that triggers the counter transfer is de?ed by the corresponding input edge bit (iedg). reset does not affect the contents of the input capture register. the result obtained from an input capture will be one greater than the value of the free-running counter on the rising edge of the internal bus clock preceding the external transition. this delay is required for internal synchronization. resolution is one count of the free-running counter, which is four internal bus clock cycles. the free-running counter contents are transferred to the input capture register on each valid signal transition whether the input capture ?g (icf) is set or clear. the input capture register always contains the free-running counter value that corresponds to the most recent input capture.after a read of the input capture register msb ($14), the counter transfer is inhibited until the lsb ($15) is also read. this characteristic causes the time used in the input capture software routine and its interaction with the main program to determine the minimum pulse period. a read of the input capture register lsb ($15) does not inhibit the free-running counter transfer since they occur on opposite edges of the internal bus clock. 6.1.4 timer control register the tcr is a read/write register containing ?e control bits. four bits control interrupts associated with each of the four ?g bits found in the timer status register. the other bit controls which edge is signi?ant to the input capture edge detector. the timer control register and the free-running counter are the only sections of the timer affected by reset. de?ition of each bit is as follows: icie - input capture interrupt enable 1 (set) input capture interrupt enabled. 0 (clear) input capture interrupt disabled. ocie - output compare interrupt enable 1 (set) output compare interrupt enabled. 0 (clear) output compare interrupt disabled. address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset tcr $0012 icie ocie toie iedg olvl 0000 00u1 tpg 47
motorola 6-6 mc68hc05bs8 timers 6 toie - timer over?w interrupt enable 1 (set) timer over?w interrupt enabled. 0 (clear) timer over?w interrupt disabled. iedg - input edge 1 (set) tcap is positive-going edge sensitive. 0 (clear) tcap is negative-going edge sensitive. when iedg is set, a positive-going edge on the tcap pin will trigger a transfer of the free-running counter value to the input capture registers. when clear, a negative-going edge triggers the transfer. olvl - output level voltage latch 1 (set) high output on tcmp pin if counter compare is true. 0 (clear) low output on tcmp pin if counter compare is true. when olvl is set high output level will be clocked into the output level register by the next successful output compare on the tcmp pin. 6.1.5 timer status register (tsr) the timer status register contains the status bits for the above three interrupt conditions - icf, ocf, and tof. accessing the timer status register satis?s the ?st condition required to clear the status bits. the remaining step is to access the register corresponding to the status bit. icf - input capture flag 1 (set) a valid input capture has occurred. 0 (clear) no input capture has occurred. this bit is set when the selected polarity of edge is detected by the input capture edge detector; an input capture interrupt will be generated, if icie is set, icf is cleared by reading the tsr and then the input capture low register ($15) address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset tsr $0013 icf ocf tof 0 0 0 0 0 uuu0 0000 tpg 48
mc68hc05bs8 motorola 6-7 timers 6 ocf - output compare flag 1 (set) a valid output compare has occurred on output compare register. 0 (clear) no output compare has occurred on output compare register. ocf will be set when the output compare register contents match that of the free-running counter; an output compare interrupt will be generated, if ocie is set. ocf is cleared by reading the tsr and then the output compare low register ($17). tof - timer over?w flag 1 (set) timer over?w has occurred. 0 (clear) no timer over?w has occurred. this bit is set when the free-running counter over?ws from $ffff to $0000; a timer over?w interrupt will occur, if toie (bit 5 in timer control register $12) is set. tof is cleared by reading the tsr and the counter low register ($19). when using the timer over?w function and reading the free-running counter at random times to measure an elapsed time, a problem may occur whereby the timer over?w ?g is unintentionally cleared if: 1) the timer status register is read or written when the tof is set, and 2) the lsb of the free-running counter is read, but not for the purpose of servicing the ?g. reading the alternate counter register instead of the counter register will avoid this potential problem. 6.1.6 programmable timer timing diagrams the relationships between the internal clock signals, the counter contents and the status of the ?g bits are shown in the following diagrams. it should be noted that the signals labelled ?nternal (processor clock, timer clocks and reset) are not available to the user. tpg 49
motorola 6-8 mc68hc05bs8 timers 6 figure 6-2 timer state timing diagram for reset figure 6-3 timer state timing diagram for input capture $fffc $fffd $fffe $ffff internal processor clock internal reset t00 t01 t10 t11 counter (16 bit) reset (external or end of por) internal timer clocks notes: reset affects only the counter register and timer control register. internal processor clock t00 t01 t10 t11 counter (16 bit) internal timer clocks $f123 $f124 $f125 $f126 $f127 $f125 $???? (see note) input edge internal capture latch input capture register input capture flag if the input edge occurs in the shaded area from one timer state t10 to the other timer state t10 the input capture ?g is set during the next state t11. note: tpg 50
mc68hc05bs8 motorola 6-9 timers 6 figure 6-4 timer state timing diagram for output compare figure 6-5 timer state diagram for timer over?w internal processor clock t00 t01 t10 t11 counter (16 bit) internal timer clocks $f455 $f456 $f457 $f458 $f459 note 1 note 2 $f457 cpu writes $f457 output compare register compare register output compare flag and tcmp note: 1. the cpu write to the compare registers may take place at any time, but a compare only occurs at the timer state t01. thus a 4-cycle difference may exist between the write to the compare register and the actual compare. 2. the output compare ?g is set at the timer state t11 that follows the comparison match ($f547 in this example). latch note 1 internal processor clock t00 t01 t10 t11 counter (16 bit) internal timer clocks $fffe $ffff $0000 $0001 $0002 note: timer overflow flag (tof) the tof bit is set at timer state t11 (transition of counter from $ffff to $0000). it is cleared by a read of the timer status register during the internal processor clock high time followed by a read of the counter low register. tpg 51
motorola 6-10 mc68hc05bs8 timers 6 6.2 core timer the core timer is a 15-stage multi-functional ripple counter which provides miscellaneous function to the mc68hc05bs8 mcu. it includes a timer over?w function, real-time interrupt, and cop watchdog. as seen in figure 6-6, the timer is driven by the internal bus clock divided by four with a ?ed prescaler. this signal drives an 8-bit ripple counter. the value of this 8-bit ripple counter can be read by the cpu at any time by accessing the ctimer counter register (ctcr) at address $09. a timer over?w function is implemented on the last stage of this counter, giving a possible interrupt at the rate of e/1024. four additional stages produces a resulting clock of e/16384, driving the real time interrupt circuit. the rti circuit consists of three divider stages with a 1 of 4 selector. the output of the rti circuit is further divided by eight to drive the optional cop watchdog timer circuit. the rti rate selector bits, and the rti and ctof enable bits and ?gs are located in the ctimer control and status register (ctcsr) at location $08. 6.2.1 ctimer counter register the core timer counter register is a read-only register which contains the current value of the 8-bit ripple counter. this counter is clocked at f op /4 and can be used for various functions including a software capture. extended time periods can be attained using the tof function to increment a temporary ram storage location thereby simulating a 16-bit (or more) counter. during the power-on reset (por) cycle, all ctimer counters are ?st cleared, the counters then count 4064 cycles before it is cleared again. after this 4064 cycles, the por circuit releases the device from reset. at this point, if reset is not asserted, the timer will start counting up from zero and normal device operation will begin. if reset is asserted anytime during operation (other than por), the counter chain will be cleared. 6.2.2 ctimer control and status register ctof - ctimer over?w 1 (set) 8-bit ripple timer over?w has occurred. 0 (clear) no 8-bit ripple timer over?w has occurred. address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset ctcr $0009 ct7 ct6 ct5 ct4 ct3 ct2 ct1 ct0 0000 0000 address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset ctcsr $0008 ctof rtif ctofe rtie 0 0 rt1 rt0 0000 0011 tpg 52
mc68hc05bs8 motorola 6-11 timers 6 this bit is set when the 8-bit ripple counter over?ws from $ff to $00; a timer over?w interrupt will occur, if tofe (bit 5) is set. tof is cleared by writing a ? to the bit. figure 6-6 core timer block diagram ctof rtif ctofe rtie rt1 rt0 internal bus ctcsr ($0008) ctimer control & status reg. ? 4 internal processor clock (e) f op ct7 ct6 ct5 ct4 ct3 ct2 ct1 ct0 ctcr ($0009) core timer counter register 8 over?w detect circuit 7-bit counter rti select circuit interrupt circuit to interrupt logic cop watchdog resetable timer ( ? 8) to reset logic 8 f op /2 2 f op /2 10 tpg 53
motorola 6-12 mc68hc05bs8 timers 6 rtif - real time interrupt flag 1 (set) a real time interrupt has occurred. 0 (clear) a real time interrupt has not occurred. when rtif is set, a cpu interrupt request is generated if rtie is set. the clock frequency that drives the rti circuit is e/12 13 . the rti rate is selectable by the rt1 and rt0 bits. rtif is cleared by writing a ? to the bit. ctofe - ctimer over?w interrupt enable 1 (set) tof interrupt is enabled. 0 (clear) tof interrupt is disabled. rtie - real time interrupt enable 1 (set) real time interrupt is enabled. 0 (clear) real time interrupt is disabled. rt1, rt0 - rate select for cop watchdog and rti see section 6.2.3 on cop watchdog reset. 6.2.3 cop watchdog reset the cop (computer operating properly) watchdog timer function is implemented by using the output of the rti selected output. the minimum cop reset rates are determined by rt0 and rt1 of ctimer control and status register. if the cop circuit times out, an internal reset is generated and the reset vector is fetched (at $3ffe & $3fff). preventing a cop time-out is achieved by periodically writing a ? to bit 0 of address $3ff0. the cop reset function is enabled after a reset, and can be disabled by writing a ? to the cop bit (bit 6) in the option register at address $001d. once disabled, it cannot be enabled except by a reset function. also, stop mode cannot be entered when the cop watchdog is enabled. table 6-1 cop reset and rti rates rt1 rt0 bus frequency, f op =2.1mhz divide ratio minimum rti rate minimum cop reset rate (rti x 7) 1/(f op /divide ratio/7) 00 2 14 7.81ms 54.7ms 01 2 15 15.6ms 109ms 10 2 16 31.2ms 219ms 11 2 17 62.5ms 438ms rt0 and rt1 should only be changed immediately after cop watchdog timer has been reset. tpg 54
mc68hc05bs8 motorola 7-1 pulse width modulation 7 7 pulse width modulation the mc68hc05bs8 has two independent pwms; one general purpose (gpwm) and one raster positioning (rspwm). they are controlled by the pwm registers located at $0010 and $0011. 7.1 general purpose pulse width modulator the gpwm consists of a comparator and a 6-bit free-running counter driven by the internal bus clock. the counter runs from $00 to $3e and rolls over back to $00. whenever the gpwm value in the gpwm register is greater than the running counter, the output of the gpwm pin will be ?igh (see figure 7-1). to reduce the occurrence of fast logic switching edges on the pcb, the gpwm output is connected to the output pin via an on chip resistor of nominal value of 5k w . in this way, for use with dc controls the rc ?ter capacitor is connected externally directly to the output. a further advantage is that the pwm logic signal has only to overcome modest on-chip capacitances and thus supply current spikes are signi?antly reduced. the gpwm output can be con?ured as an open drain output by setting ode bit in the gpwm register. it should be noted that the diode associated with the p-channel device is still connected to the output pin and therefore the normal voltage limitations apply, i.e. up to v dd . figure 7-2 shows a schematic of the gpwm output. figure 7-1 gpwm timing example 8 m s 23.5 m s 31.5 m s frame rate=32khz gpwm gpwm data = 16 = 01000 internal clock = 2mhz tpg 55
motorola 7-2 mc68hc05bs8 pulse width modulation 7 7.1.1 general purpose pulse width modulator register (gpwm) ode - open drain enable 1 (set) gpwm output con?ured as open drain output. 0 (clear) gpwm output con?ured as direct drive output. gpw5:0 - gpw data these six bits contain the pulse width modulator data for the gpwm. 7.2 raster positioning pulse width modulator the rspwm consists of a comparator and a 7-bit counter clocked by the positive edge of a clock from the rclk pin, and reset by the an active high signal from the pb7 pin. the rspwm output will be low after a counter reset, and high when the counter value matches the value in the rspwm register. figure 7-3 shows example timings. figure 7-2 gpwm output con?uration address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset gpwmr $0010 ode cre gpw5 gpw4 gpw3 gpw2 gpw1 gpw0 0000 0000 gpwmr bit 7 ode protection + v dd p n gpwm v dd r gpwm logic tpg 56
mc68hc05bs8 motorola 7-3 pulse width modulation 7 rsa and rsb are the output pins of the rspwm. they are connected such that, one of them is the pwm output waveform, while the other is always zero. this is controlled by the raster polarity bit (rsp) in the rspwm register. pb7 must be con?ured as an input port pin and the cre bit in gpwmr must be set before it can be used as the input pin for the rspwm reset signal. figure 7-4 shows a block diagram of the rspwm. figure 7-3 rspwm timing example figure 7-4 rspwm block diagram rspwm counter rspwm output counter reset (pb7) counter value matches rspwm register & & & rsa pb7 rclk rsb rspwm counter rspw6:0 rspwm logic rsp rspwmr ($0011) gpwmr bit 6 cre tpg 57
motorola 7-4 mc68hc05bs8 pulse width modulation 7 when used for raster position control, the rclk is a clock signal which is in synchronized and with a frequency of multiples to the horizontal sync signal. the counter reset signal to pb7 pin is the horizontal ? back signal. both of these signals will normally come from an osd circuit. 7.2.1 raster positioning pulse width modulator register (rspwm) rsp - raster polarity 1 (set) rsa output is zero. rspwm waveform is output on rsb. 0 (clear) rsb output is zero. rspwm waveform is output on rsa. rspw6:0 - rspwm data these 7 bits contain the pulse width modulator data for the rspwm. the rspwm output remains low after the counter reset, and turns high when the counter value matches this value. cre - clear reset enable 1 (set) pb7 pin con?ured as reset input to the rspwm. the ddr for pb7 should also be ?? 0 (clear) pb7 pin normal i/o operation. address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset rspwmr $0011 rsp rspw6 rspw5 rspw4 rspw3 rspw2 rspw1 rspw0 0000 0000 address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset gpwmr $0010 ode cre gpw5 gpw4 gpw3 gpw2 gpw1 gpw0 0000 0000 tpg 58
mc68hc05bs8 motorola 8-1 m-bus serial interface 8 8 m-bus serial interface the mc68hc05bs8 mcu has two m-bus serial interface; one is full hardware, and the other is software supported. section 8.1 to section 8.4 details the full hardware m-bus interface. section 8.5 details the software supported m-bus. m-bus (motorola bus) is a two-wire, bidirectional serial bus which provides a simple, ef?ient way for data exchange between devices. it is fully compatible with the i 2 c bus standard. this two-wire bus minimizes the interconnection between devices and eliminates the need for address decoders; resulting in less pcb traces and economic hardware structure. this bus is suitable for applications requiring communications in a short distance among a number of devices. the maximum data rate is 100kbit/s. the maximum communication length and number of devices that can be connected are limited by a maximum bus capacitance of 400pf. the m-bus system is a true multi-master bus, including arbitration to prevent data collision if two or more masters intend to control the bus simultaneously. it may be used for rapid testing and alignment of end products via external connections to an assembly-line computer. 8.1 m-bus interface features compatible with i 2 c bus standard multi-master operation 32 software programmable serial clock frequencies software selectable acknowledge bit interrupt driven byte-by-byte data transfer arbitration lost driven interrupt with automatic mode switching from master to slave calling address identi?ation interrupt generate/detect the start, stop and acknowledge signals repeated start signal generation bus busy detection tpg 59
motorola 8-2 mc68hc05bs8 m-bus serial interface 8 8.2 m-bus protocol normally, a standard communication is composed of four parts, 1) start signal, 2) slave address transmission, 3) data transfer, and 4) stop signal. they are described brie? in the following sections and illustrated in figure 8-2. figure 8-1 m-bus interface block diagram internal bus frequency divider register address comparator address register 8 men mien msta mtx txak mcf maas mbb mal srw mif rxak tx shift register rx shift register rx control tx control m-bus interrupt scl control sda control m-bus clock generator sync logic start, stop detector and arbitration start, stop generator and timing sync scl sda control register status register interrupt tpg 60
mc68hc05bs8 motorola 8-3 m-bus serial interface 8 8.2.1 start signal when the bus is free, i.e., no master device is occupying the bus (both scl and sda lines are at logic high), a master may initiate communication by sending a start signal. as shown in figure 8-2, a start signal is de?ed as a high to low transition of sda while scl is high. this signal denotes the beginning of a new data transfer (each data transfer may contain several bytes of data) and wakes up all slaves. 8.2.2 slave address transmission the ?st byte of data transfer immediately following the start signal is the slave address transmitted by the master. this is a seven bits long calling address followed by a r/w bit. the r/w bit dictates the slave of the desired direction of data transfer. only the slave with matched address will respond by sending back an acknowledge bit by pulling the sda low at the 9th clock; see figure 8-2. figure 8-2 m-bus transmission signal diagram 10 1 00011 1 0 1 00011 10 1 00011 1 0 1 00011 scl sda scl sda msb lsb msb lsb msb lsb msb lsb acknowledge bit no acknowledge start signal stop signal repeated start signal start signal stop signal acknowledge bit no acknowledge tpg 61
motorola 8-4 mc68hc05bs8 m-bus serial interface 8 8.2.3 data transfer once a successful slave addressing is achieved, the data transfer can proceed byte by byte in a direction speci?d by the r/w bit sent by the calling master. each data byte is 8 bits long. data can be changed only when scl is low and must be held stable when scl is high as shown in figure 8-2. one clock pulse is for one bit of data transfer, msb is transferred ?st. each data byte has to be followed by an acknowledge bit. hence, one complete data byte transfer requires 9 clock pulses. if the slave receiver does not acknowledge the master, the sda line should be left high by the slave, the master can then generate a stop signal to abort the data transfer or a start signal (repeated start) to commence a new calling. if the master receiver does not acknowledge the slave transmitter after one byte transmission, it means an ?nd of data to the slave. the slave shall release the sda line for the master to generate stop or start signal. 8.2.4 repeated start signal as shown in figure 8-2, a repeated start signal is to generate a start signal without ?st generating a stop signal to terminate the communication. this is used by the master to communicate with another slave or with the same slave in a different mode (transmit/receive mode) without releasing the bus. 8.2.5 stop signal the master can terminate the communication by generating a stop signal to free the bus. however, the master may generate a start signal followed by a calling command without generating a stop signal ?st. this is called repeat start. a stop signal is de?ed as a low to high transition of sda while scl is at a logical high; see figure 8-2. 8.2.6 arbitration procedure this interface circuit is a true multi-master system which allows more than one master to be connected. if two or more masters try to control the bus at the same time, a clock synchronization procedure determines the bus clock. the clock low period is equal to the longest clock low period among the masters; and the clock high period is the shortest among the masters. a data arbitration procedure determines the priority. a master will lose arbitration if it transmits a logic ? while the others transmit logic ?? the losing master will immediately switch over to slave receive mode and stops its data and clock outputs. the transition from master to slave mode will not tpg 62
mc68hc05bs8 motorola 8-5 m-bus serial interface 8 generate a stop condition. meanwhile, a software bit will be set by hardware to indicate loss of arbitration. 8.2.7 clock synchronization since wire-and logic is performed on the scl line, a high to low transition on scl line will affect the devices connected to the bus. the devices start counting their low period and once a device's clock has gone low, it will hold the scl line low until the clock high state is reached. however, the change of low to high in this device clock may not change the state of the scl line, if another device clock is still in its low period. therefore synchronized clock scl will be held low by the device which releases scl to a logic high in the last place. devices with shorter low periods enter a high wait state during this time (see figure 8-3). when all devices concerned have counted off their low period, the synchronized clock scl line will be released and go high. all of them will start counting their high periods. the ?st device to complete its high period will again pull the scl line low. 8.2.8 handshaking the clock synchronization mechanism can be used as a handshake in data transfer. slave device may hold the scl low after completion of one byte transfer (9 bits). in such case, it will halt the bus clock and force the master clock in a wait state until the slave releases the scl line. figure 8-3 clock synchronization scl1 scl2 scl internal counter reset wait start counting high period tpg 63
motorola 8-6 mc68hc05bs8 m-bus serial interface 8 8.3 m-bus registers there are ?e registers used in the m-bus interface, these are discussed in the following paragraphs. 8.3.1 m-bus address register (madr) mad1-mad7 are the slave address bits of the m-bus module. 8.3.2 m-bus frequency register (mfdr) fd0-fd4 are used for clock rate selection. the serial bit clock frequency is equal to the cpu clock divided by the divider shown in table 8-1. address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset $0039 mad7 mad6 mad5 mad4 mad3 mad2 mad1 0000 0000 address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset $003a fd4 fd3 fd2 fd1 fd0 0000 0000 table 8-1 m-bus prescaler fd4 fd3 fd2 fd1 fd0 divider fd4 fd3 fd2 fd1 fd0 divider 00000 22 10000352 00001 24 10001384 00010 28 10010448 00011 34 10011544 00100 44 10100704 00101 48 10101768 00110 56 10110896 00111 68 10111 1088 01000 88 11000 1408 01001 96 11001 1536 0 1 0 1 0 112 1 1 0 1 0 1792 0 1 0 1 1 136 1 1 0 1 1 2176 0 1 1 0 0 176 1 1 1 0 0 2816 0 1 1 0 1 192 1 1 1 0 1 3072 0 1 1 1 0 224 1 1 1 1 0 3584 0 1 1 1 1 272 1 1 1 1 1 4352 tpg 64
mc68hc05bs8 motorola 8-7 m-bus serial interface 8 for a 4mhz external crystal operation (2mhz internal operating frequency), the serial bit clock frequency of m-bus ranges from 460hz to 90,909hz. 8.3.3 m-bus control register (mcr) register bit de?itions: men - m-bus enable 1 (set) m-bus interface system enabled. 0 (clear) m-bus interface system disabled. mien - m-bus interrupt enable 1 (set) m-bus interrupt enabled. 0 (clear) m-bus interrupt disabled. this bit enables the mif (in msr) for m-bus interrupts. msta - master/slave select 1 (set) m-bus is set for master mode operation. 0 (clear) m-bus is set for slave mode operation. upon reset, this bit is cleared. when this bit is changed from 0 to 1, a start signal is generated on the bus, and the master mode is selected. when this bit is changed from 1 to 0, a stop signal is generated and the operation mode changes from master to slave. in master mode, a bit clear immediately followed by a bit set of this bit generates a repeated start signal without generating a stop signal. mtx - transmit/receive mode select 1 (set) m-bus is set for transmit mode. 0 (clear) m-bus is set for receive mode. txak - acknowledge enable 1 (set) do not send acknowledge signal. 0 (clear) send acknowledge signal at 9th clock bit. if cleared, an acknowledge signal will be sent out to the bus at the 9th clock bit after receiving one byte of data. if set, no acknowledge signal response. this is an active low control bit. address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset $003b men mien msta mtx txak sifc siic 0000 0000 tpg 65
motorola 8-8 mc68hc05bs8 m-bus serial interface 8 8.3.4 m-bus status register (msr) the mif and mal bits are software clearable; while the other bits are read only. mcf - data transfer complete 1 (set) a byte transfer has been completed. 0 (clear) a byte is being transfer. when mcf is set, the mif (m-bus interrupt) bit is also set. an m-bus interrupt is generated if the mien bit is set. maas - addressed as slave 1 (set) currently addressed as a slave. 0 (clear) not currently addressed. this maas bit is set when its own speci? address (m-bus address register) matches the calling address. when maas is set, the mif (m-bus interrupt) bit is also set. an interrupt is generated if the mien bit is set. then cpu needs to check the srw bit and set its mtx bit accordingly. writing to the m-bus control register clears this bit. mbb - bus busy 1 (set) m-bus busy. 0 (clear) m-bus idle. this bit indicates the status of the bus. when a start signal is detected, mbb is set. when a stop signal is detected, it is cleared. mal - arbitration lost 1 (set) lost arbitration in master mode. 0 (clear) no arbitration lost. this arbitration lost ?g is set when the m-bus master loses arbitration during a master transmission mode. when mal is set, the mif (m-bus interrupt) bit is also set. this bit must be cleared by software. address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset $003c mcf maas mbb mal sif srw mif rxak 1000 0001 tpg 66
mc68hc05bs8 motorola 8-9 m-bus serial interface 8 srw - slave r/w select 1 (set) read from slave, from calling master 0 (clear) write to slave from calling master. when maas is set, the r/w command bit of the calling address sent from the master is latched into this srw bit. by checking this bit, the cpu can then select slave transmit/receive mode by con?uring mtx bit of the m-bus control register. mif - m-bus interrupt 1 (set) an m-bus interrupt has occurred. 0 (clear) an m-bus interrupt has not occurred. when this bit is set, an interrupt is generated to the cpu if mien is set. this bit is set when one of the following events occurs: 1) completion of one byte of data transfer. it is set at the falling edge of the 9th clock - mcf set. 2) a match of the calling address with its own speci? address in slave mode - maas set. 3) a loss of bus arbitration - mal set. this bit must be cleared by software in the interrupt routine. rxak - receive acknowledge 1 (set) no acknowledgment signal detected. 0 (clear) acknowledgment signal detected after 8 bits data transmitted. if cleared, it indicates an acknowledge signal has been received after the completion of 8 bits data transmission on the bus. if set, no acknowledge signal has been detected at the 9th clock. this is an active low status ?g. 8.3.5 m-bus data i/o register (mdr) in master transmit mode, data written into this register is sent to the bus automatically, with the most signi?ant bit out ?st. in master receive mode, reading of this register initiates receiving of the next byte data. in slave mode, the same function applies after it has been addressed. address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset $003d md7 md6 md5 md4 md3 md2 md1 md0 uuuu uuuu tpg 67
motorola 8-10 mc68hc05bs8 m-bus serial interface 8 figure 8-4 flowchart of m-bus interrupt routine clear mif master mode? tx/rx? arbitration last byte transmitted? last byte to be read? maas=1? clear mal lost? maas=1? srw=1? set tx mode write to mdr rti set rx mode dummy read mdr tx/rx? generate stop signal ack from receiver? last 2nd byte to read? rxak=0? write to mdr generate stop signal txak=1 write to mdr read from mdr n y rx tx n y n n y y n n y y tx rx n y y n y n y n tpg 68
mc68hc05bs8 motorola 8-11 m-bus serial interface 8 8.4 programming considerations 8.4.1 initialization reset will put the m-bus control register to its default status. before the interface can be used to transfer serial data, the following initialization procedure must be carried out. 1) update frequency divider register (mfdr) to select an scl frequency. 2) update m-bus address register (madr) to de?e its own slave address. 3) set men bit of m-bus control register (mcr) to enable the m-bus interface system. 4) modify the bits of m-bus control register (mcr) to select master/slave mode, transmit/receive mode, interrupt enable or not. 8.4.2 generation of a start signal and the first byte of data transfer after completion of the initialization procedure, serial data can be transmitted by selecting the master transmit mode. if the device is connected to a multi-master bus system, the state of the m-bus busy bit (mbb) must be tested to check if the serial bus is free. if the bus is free (mbb=0), the start condition and the ?st byte (the slave address) can be sent. an example program which generates the start signal and transmits the ?st data byte (slave address) is shown below: sei ; disable interrupt chflag brset 5,msr,chflag ; check the mbb bit of the ; status register. if it is ; set, wait until it is clear txstart bset 4,mcr ; set transmit mode bset 5,mcr ; set master mode ; i.e. generate start condition lda #calling ; get the calling address sta mdr ; transmit the calling ; address cli ; enable interrupt 8.4.3 software responses after transmission or reception of a byte upon the completion of the transmission or reception of a data byte, the data transferring bit (mcf) will be set, indicating one byte communication has been ?ished. the m-bus interrupt bit (mif) will also be set to generate an m-bus interrupt if the interrupt is enabled. software must clear the tpg 69
motorola 8-12 mc68hc05bs8 m-bus serial interface 8 mif bit in the interrupt routine ?st. the mcf bit can be cleared by reading the m-bus data i/o register (mdr) in receive mode or writing to the mdr in transmit mode. software may serve the m-bus i/o in the main program by monitoring the mif bit if the interrupt is disabled. the following is an example of a software response by a master in transmit mode in the interrupt routine (see figure 8-4). isr bclr 1,msr ; clear the mif flag brclr 5,mcr,slave ; check the msta flag, ; branch if slave mode brclr 4,mcr,receive ; check the mode flag, ; branch if in receive mode brset 0,msr,end ; check ack from receiver ; if no ack, end of ; transmission transmit lda databuf ; get the next byte of data sta mdr ; transmit the data 8.4.4 generation of the stop signal a data transfer ends with a stop signal generated by the master device. a master in transmit mode can simply generate a stop signal after all the data have been transmitted. the following is an example showing how a stop condition is generated by a master in transmit mode. mastx brset 0,msr,end ; if no ack, branch to end lda txcnt ; get value from the ; transmitting counter beq end ; if no more data, branch to ; end lda databuf ; get next byte of data sta mdr ; transmit the data dec txcnt ; decrease the txcnt bra emastx ; exit end bclr 5,mcr ; generate a stop condition emastx rti ; return from interrupt if a master receiver wants to terminate a data transfer, it must inform the slave transmitter by not acknowledging the last byte of data. this can be achieved by setting the transmit acknowledge bit (txak) before reading the 2nd last byte of data. before reading the last byte of data, a stop signal must be generated ?st. the following is an example showing how a stop signal is generated by a master in receive mode. masr dec rxcnt beq enmasr ; last byte to be read lda rxcnt deca ; check last 2nd byte to be read bne nxmar ; not last one or last second tpg 70
mc68hc05bs8 motorola 8-13 m-bus serial interface 8 lamar bset 3,mcr ; last second, disable ack ; transmitting bra nxmar enmasr bclr 5,mcr ; last one, generate 'stop' ; signal nxmar lda mdr ; read data and store sta rxbuf rti 8.4.5 generation of a repeated start signal at the end of data transfer, if the master still wants to communicate on the bus, it can generate another start signal followed by another slave address without ?st generating a stop signal. a program example is as shown. restart bclr 5,mcr ; another start (restart) is bset 5,mcr ; generated by these two ; consecutive instructions lda #calling ; get the calling address sta mdr ; transmit the calling ; address 8.4.6 slave mode in the slave service routine, the master addressed as slave bit (maas) should be tested to check if a calling of its own address has been received (figure 8-4). if maas is set, software should set the transmit/receive mode select bit (mtx bit of mcr) according to the r/w command bit (srw). writing to the mcr clears the maas automatically. a data transfer may then be initiated by writing to mdr or a dummy read from mdr. in the slave transmit routine, the received acknowledge bit (rxak) must be tested before transmitting the next byte of data. rxak, if set indicates the end of data signal from the master receiver, the slave transmitter must then switch from transmit mode to receive mode by software and a dummy read must follow to release the scl line so that the master can generate a stop signal. 8.4.7 arbitration lost if more than one master want to acquire the bus simultaneously, only one master can win and the others will lose arbitration. the losing device immediately switches to slave receive mode by m-bus hardware. its data output to the sda line is stopped, but internal transmit clock still runs until the end of the data byte transmission. an interrupt occurs when this dummy byte transmission tpg 71
motorola 8-14 mc68hc05bs8 m-bus serial interface 8 is accomplished with mal=1 and msta=0. if one master attempts to start transmission while the bus is being controlled by another master, the transmission will be inhibited; the msta bit will be changed from 1 to 0 without generating stop condition; an interrupt will be generated and the mal bit set to indicate that the attempt to acquire the bus has failed. considering these cases, the slave service routine should test the mal bit ?st, and software should clear the mal bit if it is set. 8.5 software supported m-bus interface port pins pc6 and pc7 are designed with a hardware interrupt circuit for the software supported m-bus interface to detect the ?tart condition of the m-bus protocol. this interrupt uses the same interrupt vector as for the hardware m-bus interrupts, at address $3ff2 and $3ff3. the user is responsible for determining the source of the m-bus interrupt in the interrupt service routine by reading the ?gs. figure 8-5 software supported m-bus interrupt pc7/sda2 pc6/scl2 int d c r q & pc7/sda2 pc6/scl2 siic reset or sifc int interrupt request start stop tpg 72
mc68hc05bs8 motorola 8-15 m-bus serial interface 8 the software supported m-bus interrupt related control and status bits are at the following registers: sifc - software m-bus interrupt flag clear 1 (set) clear software supported m-bus interrupt ?g in msr. 0 (clear) no effect. siic - software m-bus enable 1 (set) if pc6 and pc7 satis?s the ?tart condition of the m-bus protocol, sif in the msr will be set and m-bus interrupt will be generated. 0 (clear) pc6 and pc7 pins are con?ured for standard i/o operation. sif - software supported m-bus interrupt flag 1 (set) software m-bus interrupt has occurred. 0 (clear) no software m-bus interrupt has occurred. address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset mcr $003b men mien msta mtx txak sifc siic 0000 0000 address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset msr $003c mcf maas mbb mal sif srw mif rxak 1000 0001 tpg 73
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mc68hc05bs8 motorola 9-1 sync signal processor 9 9 sync signal processor this section describes the operation of the ssp module in the mc68hc05bs8. 9.1 introduction the functions of the ssp include the following: polarity correction sync separation sync pulse reshaping sync pulse detection horizontal line counting vertical frequency counting free running signals generation in addition, an interrupt can be generated for each vertical frame at a user speci?d horizontal line number. the ssp accepts composite signals from a video processor or separate sync inputs from a host computer. for separate sync inputs, the httl output is identical to the incoming horizontal sync with negative sync polarity. the vttl output is triggered by the leading edge of the incoming sync pulse, and the sync pulse reshaper will correct the pulse width to a certain time period regardless of the incoming sync width. reassembled sync pulses are inserted for httl signal during the vertical sync period for composite sync input. the hsync, vsync, and csync inputs have internal ?ters to improve noise immunity. any pulse that is shorter than 1.5 internal bus clock periods will be regarded as a glitch, and will be ignored. note: all quoted timings in this section are based on an internal bus frequency of 2mhz, i.e. t cyc =0.5 m s, unless otherwise stated. tpg 75
motorola 9-2 mc68hc05bs8 sync signal processor 9 9.2 polarity correction the polarity correction block of the sync signal processor accepts the input sync signals and converts them to negative polarity signals, regardless of the polarity of the inputs. the following describes the methodologies used in polarity correction. 9.2.1 separate vertical sync input to test the polarity of the input sync signal, the duration of the low pulse is examined. if the low period is longer than a speci? value (512 m s or 1024t cyc ), as in the case of positive polarity input sync, the input sync will be inverted before output. for negative polarity input sync signal, it is anticipated that the duration of the low pulse would be shorter than the speci? value, and the input sync signal passes through to the output without inversion. this polarity correction is a continuous process, and the error margin is equal to the maximum permissible sync pulse width speci?d (512 m s or 1024t cyc ). at power-up or system reset, negative polarity at input is assumed. 9.2.2 separate horizontal or composite sync input since the input at hsync can be either a pure horizontal sync signal or a composite sync signal, different methodologies are used in polarity correction. unlike the polarity correction for vsync, both the high pulse and low pulse of the sync signal at hsync are examined. if the pulse, either active high or low, is longer than a certain period (8 m s or 16 t cyc ), it will be regarded as a long pulse. if there are 8 consecutive low long pulses, the input sync signal will be con?med as a positive polarity sync signal, and will be inverted. if there are 8 consecutive high long pulses, it will be con?med as a negative polarity sync signal. the operation of this module is also continuous, and the error margin is equal to the period of the pre-set number (default is 8) of horizontal sync pulses. at power-up or system reset, negative polarity at input is assumed. tpg 76
mc68hc05bs8 motorola 9-3 sync signal processor 9 9.3 sync detection the sync detector determines whether the incoming sync signal is active. both sync high and low pulse widths must be within the speci? values to be regarded as active. the respective hdet and/or vdet ?gs will be set if the hsync and vsync signals are active. 9.4 free-running pseudo sync signal generator if no active sync signals are detected, a free-running sync signal generator will be enabled. it generates a pseudo vertical sync at 63.78hz (1/(t cyc x 31360)) and a pseudo horizontal sync at 57.14khz (1/(t cyc x 35)). this set of free running sync signals replaces the inactive sync signals at the inputs and will be fed to the vttl and httl pins if the pins are selected for vttl and httl function. if both vertical and horizontal sync signals are detected (vdet and hdet are set), the sout bit must be set in order to output the processed signals. figure 9-1 sync signal polarity correction negative polarity pure horizontal sync signal positive polarity pure horizontal sync signal negative polarity composite sync signal positive polarity composite sync signal tpg 77
motorola 9-4 mc68hc05bs8 sync signal processor 9 9.5 sync separation figure 9-2 is a block diagram of the sync separator which includes the duration counters for the high and low pulses, a counter for the number of valid horizontal sync pulses, a register to hold the number of horizontal lines per frame, a logic block for horizontal and vertical sync pulse separation, a comparator, and a sync pulse insertion circuit. the low pulse duration counter examines the low pulse width of the incoming composite sync signal. if it is within the horizontal sync pulse limit (8 m s or 16 t cyc ), a horizontal sync pulse is detected, and the horizontal line counter is advanced. if the low pulse is wider than the limit, a vertical sync pulse is detected, and the content of the horizontal line counter is loaded into the horizontal line register. the low pulse duration counter then resets the horizontal line counter. the high pulse duration counter examines the high pulse width of the incoming composite sync signal. if it is longer than a speci? value (8 m s or 16 t cyc ), the vertical sync pulse has ?ished and a nish signal will be given to the sync separation logic. sync separation logic passes the csync signal to the hsync output until there is an ?qual signal from the comparator. the hsync output will then output an reassembled waveform by the sync insertion circuit to emulate the hsync pulses, and the vsync output is set to ?ow at the coming falling edge of the csync signal. after the nish signal has been sensed, the vsync output is ?ed to ?igh? and the hsync output follows the csync input again. figure 9-2 sync separator sync separation logic sync insertion circuit comparator low pulse duration counter high pulse duration counter horizontal line register horizontal line counter clk csync load reset count in out equal hsync vsync ?ish csync vertical tpg 78
mc68hc05bs8 motorola 9-5 sync signal processor 9 9.6 vertical sync pulse reshaper the vertical sync pulse width at vttl output is formatted by the vertical sync pulse reshaper, such that, its falling edge follows the input signals falling edge, and its rising edge is at the 6th falling edge of the input horizontal sync signal (hsync). notice that, if the input signal is a composite signal, the vttl pulse width will be longer, for there may not be any falling edge during the vertical sync pulse period. figure 9-3 shows the different in vttl pulse widths for different input signal formats. 9.7 sync signal counters there are two counters (horizontal line counter and vertical frequency counter) to count the number of horizontal sync pulses and the number of system clock cycles between two vertical sync pulses. these two data can be read by the cpu to check the signal frequencies and can be used to determine the video mode. notice that the value in the vertical frequency counter will be subtracted by 240 before loading into the vertical frequency register. in this way, the 9-bit register can cover a vertical frequency ranged from 42hz to 130hz. figure 9-4 shows a more detailed block diagram of these counters. figure 9-4 shows the vertical frequency counter timings. it indicates that there will be 1 count error on the reading from the register for the same vertical frequency. figure 9-3 vttl pulse widths for different input signal formats 123456 123 456 123456 vsync hsync re-shaped vttl output re-shaped vttl output re-shaped vttl output csync with h pulses during v pulse period csync without h pulses during v pulse period tpg 79
motorola 9-6 mc68hc05bs8 sync signal processor 9 9.8 vsync interrupt the cpu will process an sync signal processor vsync interrupt if the following conditions are satis?d: 1) the i-bit of the ccr is cleared, 2) the vsie bit of the interrupt line count register (ilcr) is set, and 3) the value of the horizontal line counter matches the value set in the ilcr. this interrupt will vector to the interrupt service routine located at the address speci?d by the contents of $3ff8 and $3ff9. the vsync interrupt latch will be cleared automatically by fetching of these vectors. this allows an interrupt to be generated in each vertical frame after a certain number of lines (0-127) to check the status of the monitor and conditions. figure 9-4 vertical frequency counter timing po2 vsync counter signal reset po2 ? 64 case 1 po2 ? 64 case 2 counter resets at 16 po2 cycles after falling edge of vsynin counter advances at the rising edge of the clock 1. the value of the counter will be loaded into the register before it is reset. 2. the vertical frequency counter is clocked by a po2 ? 64 clock. 3. because of the asynchronous nature between po2 and vsynin, the register will have one more count in case 2 than in case 1. tpg 80
mc68hc05bs8 motorola 9-7 sync signal processor 9 9.9 sampling pulse output the circuit is responsible for generating the sam signal for the video chip set. the sam signal is a sampling signal, which outputs a positive pulse at the vsync pulse, and outputs another positive pulse when the value of the sampling pulse register matches the horizontal line counter. the pulse width is equal to one horizontal line period. 9.10 ssp registers there are six registers associated with the sync signal processor, these are described below. 9.10.1 sync signal control and status register (sscsr) vpol - vertical sync input polarity 1 (set) vsync input is positive polarity. 0 (clear) vsync input is negative polarity. vertical sync input polarity ?g indicates the polarity of the incoming signal at the vsync input. hpol - horizontal sync input polarity 1 (set) hsync input is positive polarity. 0 (clear) hsync input is negative polarity. horizontal sync input polarity ?g indicates the polarity of the incoming signal at the hsync input. vdet - vertical sync signal detect 1 (set) an active vertical sync is detected at vsync input. 0 (clear) no vertical sync signal at vsync input; use internal generated vsync for vttl. this bit is set when an active vertical sync signal is detected on the vsync pin. if cleared, it indicates there is no active signal, and the vttl will output the internally generated vsync signal. an active vertical sync signal is de?ed as: vdet = (vsync pulse width < 1024t cyc ) ?(15.36x10 3 t cyc < vsync period < 48.128x10 3 t cyc ) address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset $000a vpol hpol vdet hdet sout insrt sin1 sin0 0000 0000 tpg 81
motorola 9-8 mc68hc05bs8 sync signal processor 9 hdet - horizontal sync signal detect 1 (set) an active horizontal sync is detected at hsync input. 0 (clear) no horizontal sync signal at hsync input; use internal generated hsync for httl. this bit is set when an active horizontal sync signal is detected on the hsync pin. if cleared, it indicates there is no active signal, and the httl will output the internally generated hsync signal. an active horizontal sync signal is de?ed as: hdet=(hsync pulse width < 16t cyc ) ?(hsync period < 128t cyc ) ?[(h line per frame < 4096) + (vdet=0)] sout - sync output select 1 (set) use processed vsync and hsync inputs for vttl and httl. 0 (clear) use internally generated sync signals for vttl and httl. when cleared, the outputs to vttl and httl are the internally generated signals. when set, the outputs are the processed input signals. this bit can only be set if both vdet and hdet are logic 1s, and will be cleared automatically if vdet or hdet is not logic ?? reset clears this bit. insrt - hsync insertion 1 (set) no inserted pulses. httl will always follow the hsync input. 0 (clear) for composite sync inputs, emulated sync pulses will be inserted into the httl signal during the vertical sync pulse. for separate sync inputs, when this hsync insertion bit is cleared, sync pulses will continue to be the hsync signal during the vertical sync pulse. for composite sync input, when this bit is cleared, emulated sync pulses will be inserted into the httl during the vertical sync pulse. in both cases, when this bit is set, there will be no inserted pulses, and httl will always follow the hsync input. reset clears this bit. sin1:sin0 - sync input source these two bits selects the source of the input sync signals. reset clears these bits. sin1 sin0 sync input source 0 0 separated sync signal through vsync and hsync inputs. 0 1 composite sync signal through hsync input. 1 x composite sync signal through csync input. tpg 82
mc68hc05bs8 motorola 9-9 sync signal processor 9 9.10.2 vertical frequency register (vfr) this 9-bit (the 9th bit is in bit 7 of lfhr at $0c) read only register is used to calculate the vertical frame frequency. a 10-bit counter counts the number of internal clocks between two vsync pulses. the counted value will then be transferred to this register. the data corresponds to the period of one vertical frame. this register can be read to determine if the frame frequency is valid, and to determine the video mode. note that data is valid only if vdet= 1. the frame frequency is calculated by 1/((vfr 1 + 240)x16t cyc ). table 9-1 shows sample values for the vertical frequency register, all vfr numbers are in hexadecimal . 9.10.3 line frequency registers (lfrs) this 12-bit read only register pair contains the number of lines in each vertical frame. an internal line counter counts the number of horizontal sync pulses between two vertical sync pulses and then transfers the counted value to this register. the data can be read to determine if the line frequency is valid, and to determine the video mode. note that data is valid only if hdet=vdet= 1. the vf8 bit is the ninth bit of the vertical frequency register (vfr). address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset vfr $000b vf7 vf6 vf5 vf4 vf3 vf2 vf1 vf0 0000 0000 table 9-1 vertical frame frequencies vfr min. freq. max. freq. vfr min. freq. max. freq. $004 127.6 128.6 $1fa 41.8 41.9 $005 127.0 128.1 $1fb 41.8 41.8 $006 126.5 127.6 $1fc 41.7 41.8 $007 126.0 127.0 $1fd 41.7 41.8 address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset lfhr $000c vf8 lf11 lf10 lf9 lf8 0000 0000 lflr $000d lf7 lf6 lf5 lf4 lf3 lf2 lf1 lf0 0000 0000 tpg 83
motorola 9-10 mc68hc05bs8 sync signal processor 9 9.10.4 interrupt line count register (ilcr) this is a read/write register containing the line number for which the vertical sync interrupt is to be generated. interrupt will be generated if vsie bit is set, i bit in ccr is cleared, and the internal line counter value matches the setting in this register after the vsync pulse. the vsync interrupt vectors are at $3ff8 and $3ff9, and the interrupt latch is cleared by fetching the interrupt vectors. vsie - vsync interrupt enable this bit enables and disables the vsync interrupt. 1 (set) vsync interrupt enabled. 0 (clear) vsync interrupt disabled. lc6:0 - line count for vsync interrupt these 7 bits store the line number for which the vsync interrupt will occur. the number is ranged from 0 to 127. 9.10.5 sampling pulse register (spr) this read/write register contains the line number for which the sampling pulse in sam output to be generated. the line number is ranged from 0 to 127. sampling pulses are produced when there is a vsync pulse, or this register matches the horizontal line counter. 9.11 system operation the sync processor accepts sync signals from the main computer; the signals can either be separate hsync and vsync or composite sync through hsync input. polarity correction is performed before the sync signals go any further into the system. the sync pulse detection blocks will continuously monitor the signal, to see if it is active. if the signal is not active, the circuit will switch to output the internally generated clock signal. this will protect the circuits behind from being damaged by an inactive signal. address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset ilcr $000e vsie lc6 lc5 lc4 lc3 lc2 lc1 lc0 0000 0010 address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset spr $000f sp6 sp5 sp4 sp3 sp2 sp1 sp0 0000 0010 tpg 84
mc68hc05bs8 motorola 9-11 sync signal processor 9 figure 9-5 shows an example of ssp operation. figure 9-5 example of ssp operation n y set spr and ilcr as desired hdet, vdet=1? set video mode set sout sin1, sin0=? start valid sync signal found continue with main program 0, 0 0, 1 1, 0 no valid sync signals found continue with corresponding program set sin1, sin0=1, 0 send signal to video chip for the sync-on-green signal set sin1, sin0=0, 1 delay for the sync signals to stable and detection tpg 85
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mc68hc05bs8 motorola 10-1 cpu core and instruction set 10 10 cpu core and instruction set this section provides a description of the cpu core registers, the instruction set and the addressing modes of the mc68hc05bs8. 10.1 registers the mcu contains ?e registers, as shown in the programming model of figure 10-1. the interrupt stacking order is shown in figure 10-2. 10.1.1 accumulator (a) the accumulator is a general purpose 8-bit register used to hold operands and results of arithmetic calculations or data manipulations. figure 10-1 programming model accumulator index register program counter stack pointer condition code register carry / borrow zero negative interrupt mask half carry 70 70 15 7 0 0 15 7 0 0 0 0 0 0 0 0 1 1 70 1 1 1 h i n z c 0 0 tpg 87
motorola 10-2 mc68hc05bs8 cpu core and instruction set 10 10.1.2 index register (x) the index register is an 8-bit register, which can contain the indexed addressing value used to create an effective address. the index register may also be used as a temporary storage area. 10.1.3 program counter (pc) the program counter is a 16-bit register, which contains the address of the next byte to be fetched. 10.1.4 stack pointer (sp) the stack pointer is a 16-bit register, which contains the address of the next free location on the stack. during an mcu reset or the reset stack pointer (rsp) instruction, the stack pointer is set to location $00ff. the stack pointer is then decremented as data is pushed onto the stack and incremented as data is pulled from the stack. when accessing memory, the ten most signi?ant bits are permanently set to 0000000011. these ten bits are appended to the six least signi?ant register bits to produce an address within the range of $00c0 to $00ff. subroutines and interrupts may use up to 64 (decimal) locations. if 64 locations are exceeded, the stack pointer wraps around and overwrites the previously stored information. a subroutine call occupies two locations on the stack; an interrupt uses ?e locations. 10.1.5 condition code register (ccr) the ccr is a 5-bit register in which four bits are used to indicate the results of the instruction just executed, and the ?th bit indicates whether interrupts are masked. these bits can be individually tested by a program, and speci? actions can be taken as a result of their state. each bit is explained in the following paragraphs. half carry (h) this bit is set during add and adc operations to indicate that a carry occurred between bits 3 and 4. figure 10-2 stacking order condition code register accumulator index register program counter high program counter low 70 stack unstack decreasing memory address increasing memory address interrupt return tpg 88
mc68hc05bs8 motorola 10-3 cpu core and instruction set 10 interrupt (i) when this bit is set, all maskable interrupts are masked. if an interrupt occurs while this bit is set, the interrupt is latched and remains pending until the interrupt bit is cleared. negative (n) when set, this bit indicates that the result of the last arithmetic, logical, or data manipulation was negative. zero (z) when set, this bit indicates that the result of the last arithmetic, logical, or data manipulation was zero. carry/borrow (c) when set, this bit indicates that a carry or borrow out of the arithmetic logical unit (alu) occurred during the last arithmetic operation. this bit is also affected during bit test and branch instructions and during shifts and rotates. 10.2 instruction set the mcu has a set of 62 basic instructions. they can be grouped into ?e different types as follows: register/memory read/modify/write branch bit manipulation control the following paragraphs brie? explain each type. all the instructions within a given type are presented in individual tables. this mcu uses all the instructions available in the m146805 cmos family plus one more: the unsigned multiply (mul) instruction. this instruction allows unsigned multiplication of the contents of the accumulator (a) and the index register (x). the high-order product is then stored in the index register and the low-order product is stored in the accumulator. a detailed definition of the mul instruction is shown in table 10-1. tpg 89
motorola 10-4 mc68hc05bs8 cpu core and instruction set 10 10.2.1 register/memory instructions most of these instructions use two operands. the ?st operand is either the accumulator or the index register. the second operand is obtained from memory using one of the addressing modes. the jump unconditional (jmp) and jump to subroutine (jsr) instructions have no register operand. refer to table 10-2 for a complete list of register/memory instructions. 10.2.2 branch instructions these instructions cause the program to branch if a particular condition is met; otherwise, no operation is performed. branch instructions are two-byte instructions. refer to table 10-3. 10.2.3 bit manipulation instructions the mcu can set or clear any writable bit that resides in the ?st 256 bytes of the memory space (page 0). all port data and data direction registers, timer and serial interface registers, control/status registers and a portion of the on-chip ram reside in page 0. an additional feature allows the software to test and branch on the state of any bit within these locations. the bit set, bit clear, bit test and branch functions are all implemented with single instructions. for the test and branch instructions, the value of the bit tested is also placed in the carry bit of the condition code register. refer to table 10-4. 10.2.4 read/modify/write instructions these instructions read a memory location or a register, modify or test its contents, and write the modi?d value back to memory or to the register. the test for negative or zero (tst) instruction is an exception to this sequence of reading, modifying and writing, since it does not modify the value. refer to table 10-5 for a complete list of read/modify/write instructions. 10.2.5 control instructions these instructions are register reference instructions and are used to control processor operation during program execution. refer to table 10-6 for a complete list of control instructions. 10.2.6 tables tables for all the instruction types listed above follow. in addition there is a complete alphabetical listing of all the instructions (see table 10-7), and an opcode map for the instruction set of the m68hc05 mcu family (see table 10-8). tpg 90
mc68hc05bs8 motorola 10-5 cpu core and instruction set 10 table 10-1 mul instruction operation x:a ? x*a description multiplies the eight bits in the index register by the eight bits in the accumulator and places the 16-bit result in the concatenated accumulator and index register. condition codes h : cleared i : not affected n : not affected z : not affected c : cleared source mul form addressing mode cycles bytes opcode inherent 11 1 $42 table 10-2 register/memory instructions addressing modes immediate direct extended indexed (no offset) indexed (8-bit offset) indexed (16-bit offset) function mnemonic opcode # bytes # cycles opcode # bytes # cycles opcode # bytes # cycles opcode # bytes # cycles opcode # bytes # cycles opcode # bytes # cycles load a from memory lda a6 2 2 b6 2 3 c6 3 4 f6 1 3 e6 2 4 d6 3 5 load x from memory ldx ae 2 2 be 2 3 ce 3 4 fe 1 3 ee 2 4 de 3 5 store a in memory sta b7 2 4 c7 3 5 f7 1 4 e7 2 5 d7 3 6 store x in memory stx bf 2 4 cf 3 5 ff 1 4 ef 2 5 df 3 6 add memory to a add ab 2 2 bb 2 3 cb 3 4 fb 1 3 eb 2 4 db 3 5 add memory and carry to a adc a9 2 2 b9 2 3 c9 3 4 f9 1 3 e9 2 4 d9 3 5 subtract memory sub a0 2 2 b0 2 3 c0 3 4 f0 1 3 e0 2 4 d0 3 5 subtract memory from a with borrow sbc a2 2 2 b2 2 3 c2 3 4 f2 1 3 e2 2 4 d2 3 5 and memory with a and a4 2 2 b4 2 3 c4 3 4 f4 1 3 e4 2 4 d4 3 5 or memory with a ora aa 2 2 ba 2 3 ca 3 4 fa 1 3 ea 2 4 da 3 5 exclusive or memory with a eor a8 2 2 b8 2 3 c8 3 4 f8 1 3 e8 2 4 d8 3 5 arithmetic compare a with memory cmp a1 2 2 b1 2 3 c1 3 4 f1 1 3 e1 2 4 d1 3 5 arithmetic compare x with memory cpx a3 2 2 b3 2 3 c3 3 4 f3 1 3 e3 2 4 d3 3 5 bit test memory with a (logical compare) bit a5 2 2 b5 2 3 c5 3 4 f5 1 3 e5 2 4 d5 3 5 jump unconditional jmp bc 2 2 cc 3 3 fc 1 2 ec 2 3 dc 3 4 jump to subroutine jsr bd 2 5 cd 3 6 fd 1 5 ed 2 6 dd 3 7 tpg 91
motorola 10-6 mc68hc05bs8 cpu core and instruction set 10 table 10-3 branch instructions relative addressing mode function mnemonic opcode # bytes # cycles branch always bra 20 2 3 branch never brn 21 2 3 branch if higher bhi 22 2 3 branch if lower or same bls 23 2 3 branch if carry clear bcc 24 2 3 (branch if higher or same) (bhs) 24 2 3 branch if carry set bcs 25 2 3 (branch if lower) (blo) 25 2 3 branch if not equal bne 26 2 3 branch if equal beq 27 2 3 branch if half carry clear bhcc 28 2 3 branch if half carry set bhcs 29 2 3 branch if plus bpl 2a 2 3 branch if minus bmi 2b 2 3 branch if interrupt mask bit is clear bmc 2c 2 3 branch if interrupt mask bit is set bms 2d 2 3 branch if interrupt line is low bil 2e 2 3 branch if interrupt line is high bih 2f 2 3 branch to subroutine bsr ad 2 6 table 10-4 bit manipulation instructions addressing modes bit set/clear bit test and branch function mnemonic opcode # bytes # cycles opcode # bytes # cycles branch if bit n is set brset n (n=0?) 2? 3 5 branch if bit n is clear brclr n (n=0?) 01+2? 3 5 set bit n bset n (n=0?) 10+2? 2 5 clear bit n bclr n (n=0?) 11+2? 2 5 tpg 92
mc68hc05bs8 motorola 10-7 cpu core and instruction set 10 table 10-5 read/modify/write instructions addressing modes inherent (a) inherent (x) direct indexed (no offset) indexed (8-bit offset) function mnemonic opcode # bytes # cycles opcode # bytes # cycles opcode # bytes # cycles opcode # bytes # cycles opcode # bytes # cycles increment inc 4c 1 3 5c 1 3 3c 2 5 7c 1 5 6c 2 6 decrement dec 4a 1 3 5a 1 3 3a 2 5 7a 1 5 6a 2 6 clear clr 4f 1 3 5f 1 3 3f 2 5 7f 1 5 6f 2 6 complement com 43 1 3 53 1 3 33 2 5 73 1 5 63 2 6 negate (twos complement) neg 40 1 3 50 1 3 30 2 5 70 1 5 60 2 6 rotate left through carry rol 49 1 3 59 1 3 39 2 5 79 1 5 69 2 6 rotate right through carry ror 46 1 3 56 1 3 36 2 5 76 1 5 66 2 6 logical shift left lsl 48 1 3 58 1 3 38 2 5 78 1 5 68 2 6 logical shift right lsr 44 1 3 54 1 3 34 2 5 74 1 5 64 2 6 arithmetic shift right asr 47 1 3 57 1 3 37 2 5 77 1 5 67 2 6 test for negative or zero tst 4d 1 3 5d 1 3 3d 2 4 7d 1 4 6d 2 5 multiply mul 42 1 11 table 10-6 control instructions inherent addressing mode function mnemonic opcode # bytes # cycles transfer a to x tax 97 1 2 transfer x to a txa 9f 1 2 set carry bit sec 99 1 2 clear carry bit clc 98 1 2 set interrupt mask bit sei 9b 1 2 clear interrupt mask bit cli 9a 1 2 software interrupt swi 83 1 10 return from subroutine rts 81 1 6 return from interrupt rti 80 1 9 reset stack pointer rsp 9c 1 2 no-operation nop 9d 1 2 stop stop 8e 1 2 wait wait 8f 1 2 tpg 93
motorola 10-8 mc68hc05bs8 cpu core and instruction set 10 table 10-7 instruction set mnemonic addressing modes condition codes inh imm dir ext rel ix ix1 ix2 bsc btb h i n z c adc add and asl asr bcc bclr bcs beq bhcc bhcs bhi bhs bih bil bit blo bls bmc bmi bms bne bpl bra brn brclr brset bset bsr clc 0 cli 0 clr 01 cmp condition code symbols h half carry (from bit 3) tested and set if true, cleared otherwise i interrupt mask not affected n negate (sign bit) ? load ccr from stack z zero 0 cleared c carry/borrow 1 set not implemented address mode abbreviations bsc bit set/clear imm immediate btb bit test & branch ix indexed (no offset) dir direct ix1 indexed, 1 byte offset ext extended ix2 indexed, 2 byte offset inh inherent rel relative tpg 94
mc68hc05bs8 motorola 10-9 cpu core and instruction set 10 com 1 cpx dec eor inc jmp jsr lda ldx lsl lsr 0 mul 00 neg nop ora rol ror rsp rti ????? rts sbc sec 1 sei 1 sta stop 0 stx sub swi 1 tax tst txa wait 0 table 10-7 instruction set (continued) mnemonic addressing modes condition codes inh imm dir ext rel ix ix1 ix2 bsc btb h i n z c condition code symbols h half carry (from bit 3) tested and set if true, cleared otherwise i interrupt mask not affected n negate (sign bit) ? load ccr from stack z zero 0 cleared c carry/borrow 1 set not implemented address mode abbreviations bsc bit set/clear imm immediate btb bit test & branch ix indexed (no offset) dir direct ix1 indexed, 1 byte offset ext extended ix2 indexed, 2 byte offset inh inherent rel relative tpg 95
motorola 10-10 mc68hc05bs8 cpu core and instruction set 10 table 10-8 m68hc05 opcode map bit manipulation branch read/modify/write control register/memory btb bsc rel dir inh inh ix1 ix inh inh imm dir ext ix2 ix1 ix high 0123456789abcdef high low 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 low 0 0000 553533659 234543 0 0000 brset0 bset0 bra neg nega negx neg neg rti sub sub sub sub sub sub 3 btb 2 bsc 2 rel 2 dir 1 inh 1 inh 2 ix1 1 ix 1 inh 2 imm 2 dir 3 ext 3 ix2 2 ix1 1 ix 1 0001 553 6 234543 1 0001 brclr0 bclr0 brn rts cmp cmp cmp cmp cmp cmp 3 btb 2 bsc 2 rel 1 inh 2 imm 2 dir 3 ext 3 ix2 2 ix1 1 ix 2 0010 553 11 234543 2 0010 brset1 bset1 bhi mul sbc sbc sbc sbc sbc sbc 3 btb 2 bsc 2 rel 1 inh 2 imm 2 dir 3 ext 3 ix2 2 ix1 1 ix 3 0011 5535336510 234543 3 0011 brclr1 bclr1 bls com coma comx com com swi cpx cpx cpx cpx cpx cpx 3 btb 2 bsc 2 rel 2 dir 1 inh 1 inh 2 ix1 1 ix 1 inh 2 imm 2 dir 3 ext 3 ix2 2 ix1 1 ix 4 0100 55353365 234543 4 0100 brset2 bset2 bcc lsr lsra lsrx lsr lsr and and and and and and 3 btb 2 bsc 2 rel 2 dir 1 inh 1 inh 2 ix1 1 ix 2 imm 2 dir 3 ext 3 ix2 2 ix1 1 ix 5 0101 553 234543 5 0101 brclr2 bclr2 bcs bit bit bit bit bit bit 3 btb 2 bsc 2 rel 2 imm 2 dir 3 ext 3 ix2 2 ix1 1 ix 6 0110 55353365 234543 6 0110 brset3 bset3 bne ror rora rorx ror ror lda lda lda lda lda lda 3 btb 2 bsc 2 rel 2 dir 1 inh 1 inh 2 ix1 1 ix 2 imm 2 dir 3 ext 3 ix2 2 ix1 1 ix 7 0111 55353365 2 45654 7 0111 brclr3 bclr3 beq asr asra asrx asr asr tax sta sta sta sta sta 3 btb 2 bsc 2 rel 2 dir 1 inh 1 inh 2 ix1 1 ix 1 inh 2 dir 3 ext 3 ix2 2 ix1 1 ix 8 1000 55353365 2234543 8 1000 brset4 bset4 bhcc lsl lsla lslx lsl lsl clc eor eor eor eor eor eor 3 btb 2 bsc 2 rel 2 dir 1 inh 1 inh 2 ix1 1 ix 1 inh 2 imm 2 dir 3 ext 3 ix2 2 ix1 1 ix 9 1001 55353365 2234543 9 1001 brclr4 bclr4 bhcs rol rola rolx rol rol sec adc adc adc adc adc adc 3 btb 2 bsc 2 rel 2 dir 1 inh 1 inh 2 ix1 1 ix 1 inh 2 imm 2 dir 3 ext 3 ix2 2 ix1 1 ix a 1010 55353365 2234543 a 1010 brset5 bset5 bpl dec deca decx dec dec cli ora ora ora ora ora ora 3 btb 2 bsc 2 rel 2 dir 1 inh 1 inh 2 ix1 1 ix 1 inh 2 imm 2 dir 3 ext 3 ix2 2 ix1 1 ix b 1011 553 2234543 b 1011 brclr5 bclr5 bmi sei add add add add add add 3 btb 2 bsc 2 rel 1 inh 2 imm 2 dir 3 ext 3 ix2 2 ix1 1 ix c 1100 55353365 2 23432 c 1100 brset6 bset6 bmc inc inca incx inc inc rsp jmp jmp jmp jmp jmp 3 btb 2 bsc 2 rel 2 dir 1 inh 1 inh 2 ix1 1 ix 1 inh 2 dir 3 ext 3 ix2 2 ix1 1 ix d 1101 55343354 2656765 d 1101 brclr6 bclr6 bms tst tsta tstx tst tst nop bsr jsr jsr jsr jsr jsr 3 btb 2 bsc 2 rel 2 dir 1 inh 1 inh 2 ix1 1 ix 1 inh 2 rel 2 dir 3 ext 3 ix2 2 ix1 1 ix e 1110 553 2 234543 e 1110 brset7 bset7 bil stop ldx ldx ldx ldx ldx ldx 3 btb 2 bsc 2 rel 1 inh 2 imm 2 dir 3 ext 3 ix2 2 ix1 1 ix f 1111 5535336522 45654 f 1111 brclr7 bclr7 bih clr clra clrx clr clr wait txa stx stx stx stx stx 3 btb 2 bsc 2 rel 2 dir 1 inh 1 inh 2 ix1 1 ix 1 inh 1 inh 2 dir 3 ext 3 ix2 2 ix1 1 ix f 1111 3 0 0000 sub 1ix opcode in hexadecimal opcode in binary address mode cycles bytes mnemonic legend abbreviations for address modes and registers bsc btb dir ext inh imm ix ix1 ix2 rel a x bit set/clear bit test and branch direct extended inherent immediate indexed (no offset) indexed, 1 byte (8-bit) offset indexed, 2 byte (16-bit) offset relative accumulator index register not implemented tpg 96
mc68hc05bs8 motorola 10-11 cpu core and instruction set 10 10.3 addressing modes ten different addressing modes provide programmers with the ?xibility to optimize their code for all situations. the various indexed addressing modes make it possible to locate data tables, code conversion tables and scaling tables anywhere in the memory space. short indexed accesses are single byte instructions; the longest instructions (three bytes) enable access to tables throughout memory. short absolute (direct) and long absolute (extended) addressing are also included. one or two byte direct addressing instructions access all data bytes in most applications. extended addressing permits jump instructions to reach all memory locations. the term ?ffective address (ea) is used in describing the various addressing modes. the effective address is de?ed as the address from which the argument for an instruction is fetched or stored. the ten addressing modes of the processor are described below. parentheses are used to indicate ?ontents of the location or register referred to. for example, (pc) indicates the contents of the location pointed to by the pc (program counter). an arrow indicates ?s replaced by and a colon indicates concatenation of two bytes. for additional details and graphical illustrations, refer to the m6805 hmos/m146805 cmos family microcomputer/ microprocessor user's manual or to the m68hc05 applications guide . 10.3.1 inherent in the inherent addressing mode, all the information necessary to execute the instruction is contained in the opcode. operations specifying only the index register or accumulator, as well as the control instruction, with no other arguments are included in this mode. these instructions are one byte long. 10.3.2 immediate in the immediate addressing mode, the operand is contained in the byte immediately following the opcode. the immediate addressing mode is used to access constants that do not change during program execution (e.g. a constant used to initialize a loop counter). ea = pc+1; pc ? pc+2 10.3.3 direct in the direct addressing mode, the effective address of the argument is contained in a single byte following the opcode byte. direct addressing allows the user to directly address the lowest 256 bytes in memory with a single two-byte instruction. ea = (pc+1); pc ? pc+2 address bus high ? 0; address bus low ? (pc+1) tpg 97
motorola 10-12 mc68hc05bs8 cpu core and instruction set 10 10.3.4 extended in the extended addressing mode, the effective address of the argument is contained in the two bytes following the opcode byte. instructions with extended addressing mode are capable of referencing arguments anywhere in memory with a single three-byte instruction. when using the motorola assembler, the user need not specify whether an instruction uses direct or extended addressing. the assembler automatically selects the short form of the instruction. ea = (pc+1):(pc+2); pc ? pc+3 address bus high ? (pc+1); address bus low ? (pc+2) 10.3.5 indexed, no offset in the indexed, no offset addressing mode, the effective address of the argument is contained in the 8-bit index register. this addressing mode can access the ?st 256 memory locations. these instructions are only one byte long. this mode is often used to move a pointer through a table or to hold the address of a frequently referenced ram or i/o location. ea = x; pc ? pc+1 address bus high ? 0; address bus low ? x 10.3.6 indexed, 8-bit offset in the indexed, 8-bit offset addressing mode, the effective address is the sum of the contents of the unsigned 8-bit index register and the unsigned byte following the opcode. therefore the operand can be located anywhere within the lowest 511 memory locations. this addressing mode is useful for selecting the mth element in an n element table. ea = x+(pc+1); pc ? pc+2 address bus high ? k; address bus low ? x+(pc+1) where k = the carry from the addition of x and (pc+1) 10.3.7 indexed, 16-bit offset in the indexed, 16-bit offset addressing mode, the effective address is the sum of the contents of the unsigned 8-bit index register and the two unsigned bytes following the opcode. this address mode can be used in a manner similar to indexed, 8-bit offset except that this three-byte instruction allows tables to be anywhere in memory. as with direct and extended addressing, the motorola assembler determines the shortest form of indexed addressing. ea = x+[(pc+1):(pc+2)]; pc ? pc+3 address bus high ? (pc+1)+k; address bus low ? x+(pc+2) where k = the carry from the addition of x and (pc+2) tpg 98
mc68hc05bs8 motorola 10-13 cpu core and instruction set 10 10.3.8 relative the relative addressing mode is only used in branch instructions. in relative addressing, the contents of the 8-bit signed byte (the offset) following the opcode are added to the pc if, and only if, the branch conditions are true. otherwise, control proceeds to the next instruction. the span of relative addressing is from ?26 to +129 from the opcode address. the programmer need not calculate the offset when using the motorola assembler, since it calculates the proper offset and checks to see that it is within the span of the branch. ea = pc+2+(pc+1); pc ? ea if branch taken; otherwise ea = pc ? pc+2 10.3.9 bit set/clear in the bit set/clear addressing mode, the bit to be set or cleared is part of the opcode. the byte following the opcode speci?s the address of the byte in which the speci?d bit is to be set or cleared. any read/write bit in the ?st 256 locations of memory, including i/o, can be selectively set or cleared with a single two-byte instruction. ea = (pc+1); pc ? pc+2 address bus high ? 0; address bus low ? (pc+1) 10.3.10 bit test and branch the bit test and branch addressing mode is a combination of direct addressing and relative addressing. the bit to be tested and its condition (set or clear) is included in the opcode. the address of the byte to be tested is in the single byte immediately following the opcode byte (ea1). the signed relative 8-bit offset in the third byte (ea2) is added to the pc if the speci?d bit is set or cleared in the speci?d memory location. this single three-byte instruction allows the program to branch based on the condition of any readable bit in the ?st 256 locations of memory. the span of branch is from ?25 to +130 from the opcode address. the state of the tested bit is also transferred to the carry bit of the condition code register. ea1 = (pc+1); pc ? pc+2 address bus high ? 0; address bus low ? (pc+1) ea2 = pc+3+(pc+2); pc ? ea2 if branch taken; otherwise pc ? pc+3 tpg 99
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mc68hc05bs8 motorola 11-1 low power modes 11 11 low power modes the mc68hc05bs8 has two low-power operating modes: the stop mode and wait mode. these two modes help to reduce the power required for the mcu by stopping various internal clocks and/or the on-chip oscillator. the ?w of the stop and wait modes is shown in figure 11-1. 11.1 stop mode the stop instruction places the mcu in its lowest power consumption mode. in the stop mode the internal oscillator is turned off, halting all internal processing. when the cpu enters stop mode, the i-bit in the condition code register will be cleared automatically. this enables the external hardware interrupt to ?ake-up the mcu. all other registers and memory remain unchanged. all input/output lines remain unchanged. the mcu can be brought out of the stop mode only by a hardware interrupt or an externally generated reset (por or reset ). when exiting the stop mode the internal oscillator will resume after a 4064 internal processor clock cycle oscillator stabilization delay. note: the stop mode cannot be entered if the cop watchdog timer is running. 11.2 wait mode the wait instruction places the mcu in a low power mode. in the wait mode the internal processor clock is halted, suspending all processor and internal bus activity. other internal clocks remain active, permitting interrupts to be generated from the sub-systems, or a reset generated from the cop watchdog timer. the timer may be used to generate a periodic exit from the wait mode. execution of the wait instruction automatically clears the i-bit in the condition code register, so that any hardware interrupt can ?ake-up the mcu. all other registers, memory, and input/output lines remain in their previous states. tpg 101
motorola 11-2 mc68hc05bs8 low power modes 11 figure 11-1 stop and wait flowchart y external n stop stop external oscillator; stop internal timer clock; reset start-up delay. stop internal processor clock, clear i-bit in ccr reset? external h/w reset? 1. fetch reset vector or 2. service interrupt a. stack b. set i-bit c. vector to interrupt routine n y restart external oscillator; stabilization delay. end of start-up delay? n y restart internal processor clock wait external oscillator active and internal timer clock active stop internal processor clock, clear i-bit in ccr external reset? internal cop reset? external h/w reset? internal interrupt? n n n n y y y y tpg 102
mc68hc05bs8 motorola 11-3 low power modes 11 11.3 data retention mode the contents of ram and cpu registers are retained at supply voltages as low as 2.0v dc. this is called the data-retention mode where the data is held, but the device is not guaranteed to operate. the reset pin must be held low during data-retention mode. 11.4 cop watchdog timer considerations the cop watchdog timer is enabled by default after a reset, and can be disabled by writing a ? to the cop bit in the option register (bit 6 at address $1d). once enabled, any execution of the stop instruction will be executed as a wait instruction. that is, the stop mode cannot be entered if the cop watchdog timer is enabled. if the cop watchdog timer is enabled, the cop will reset the mcu when it times out. for a system that must have intentional uses of the wait mode, care must be taken to prevent such situations from happening during normal operations by arranging timely interrupts to reset the cop watchdog timer. tpg 103
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mc68hc05bs8 motorola 12-1 operating modes 12 12 operating modes the mc68hc05bs8/ mc68hc705bs8 mcu has two modes of operation, the user mode and the self-check/ bootstrap mode. figure 12-1 shows the ?wchart of entry to these two modes, and table 12-1 shows operating mode selection. figure 12-1 flowchart of mode entering pb6 = v dd ? reset irq self-check/ mode user mode 5v 9v ? n y y (normal mode) bootstrap self-check mode is for mc68hc05bs8 bootstrap mode is for mc68hc705bs8 note: tpg 105
motorola 12-2 mc68hc05bs8 operating modes 12 12.1 user mode (normal operation) the normal operating mode of the mc68hc05bs8/ mc68hc705bs8 is the user mode. the user mode will be entered if the reset line is brought low, and the irq pin is within its normal operational range (v ss to v dd ), the rising edge of the reset will cause the mcu to enter the user mode. 12.2 self-check mode the self-check mode is provided on the mc68hc05bs8 for the user to check device functions with an on-chip self-check program masked at location $1600 to $17ff under minimum hardware support. the self-check schematic is shown in figure 12-3. figure 12-2 is the criteria to enter self-check mode, where pb6s condition is latched within ?st two clock cycles after the rising edge of the reset. pb6 can then be used for other purposes. after entering the self-check mode, cpu branches to the self-check program and carries out the self-check. self-check is a repetitive test, i.e. if all parts are checked to be good, the cpu will repeat the self-check again. therefore, the leds attached to port a will be ?shing if the device is good; else the combination of leds on-off pattern can show what part of the device is suspected to be bad. table 12-2 lists the leds on-off patterns and their corresponding indications. table 12-1 mode selection reset irq pb6 mode v ss to v dd v ss to v dd user +9v rising edge* v dd self-check/ bootstrap * minimum hold time should be 2 clock cycles, after that it can be used as a normal irq function pin. figure 12-2 self-check mode timing 5v 5v 9v pb6 irq reset +5v +5v +9v tpg 106
mc68hc05bs8 motorola 12-3 operating modes 12 figure 12-3 mc68hc05bs8 self-test circuit osc1 osc2 mc68hc05bs8 2m 36p 4mhz +5v 330 330 reset irq 36p +5v vss 330 330 pc0 pc1 pc2 pc3 pc4 pc5 pc6 pc7 pb0 pb1 pb2 pb3 pb4 pb5 pb6 pb7 pa0 pa4 pa1 pa5 pa2 pa6 pa7 +9v 10 m 10k + reset vdd 500 4k7 mps3646 10k +5v 1n4148 pa3 vttl httl sam tcmp +5v 500 tcap csync vsync hsync sda scl rclk rsa rsb gpwm +5v 500 tpg 107
motorola 12-4 mc68hc05bs8 operating modes 12 12.3 bootstrap mode the bootstrap mode is provided in the eprom part (mc68hc705bs8) as a mean of self-programming its eprom with minimal circuitry. it is entered on the rising edge of reset if irq pin is at 1.8v dd and pb6 is at logic one. reset must be held low for 4064 cycles after por (power-on reset) or for a time t rl for any other reset. the user eprom consists of 10k-bytes, from location $1800 to $3fdf. refer to appendix a for further details on mc68hc705bs8. table 12-2 self-check report pa4 pa3 pa1 pa0 remarks flashing o.k. (self-check is on-going) 1 1 1 1 bad port a 1 1 1 0 bad port b 1 1 0 1 bad port c 1 1 0 0 bad ram 1 0 1 1 bad rom 1 0 1 0 bad irq 1 0 0 1 bad kbi 0 1 1 1 bad ctimer 0 1 1 0 bad gpwm 1=led off, 0=led on tpg 108
mc68hc05bs8 motorola 13-1 electrical specifications 13 13 electrical specifications this section contains the electrical speci?ations for mc68hc05bs8. 13.1 maximum ratings this device contains circuitry to protect the inputs against damage due to high static voltages or electric ?lds. however, it is advised that normal precautions should be taken to avoid application of any voltage higher than the maximum rated voltages to this high impedance circuit. for proper operation it is recommended that v in and v out be constrained to the range v ss (v in or v out ) v dd . reliability of operation is enhanced if unused inputs are connected to an appropriate logic voltage level (e.g. either v ss or v dd ). 13.2 thermal characteristics (voltages referenced to v ss ) ratings symbol value unit supply voltage v dd ?.3 to +7.0 v input voltage v in v ss ?.3 to v dd +0.3 v irq v in v ss ?.3 to 2xv dd +0.3 v current drain per pin excluding v dd and v ss i d 25 ma operating temperature t a 0 to 70 c storage temperature range t stg ?5 to +150 c characteristics symbol value unit thermal resistance - plastic 44-pin qfp package q ja 60 c/w tpg 109
motorola 13-2 mc68hc05bs8 electrical specifications 13 13.3 dc electrical characteristics table 13-1 dc electrical characteristics for mc68hc05bs8 (v dd =5.0vdc 10%, v ss =0vdc, temperature range=0 to 70 c) characteristics symbol minimum typical maximum unit output voltage i load = ?0 m a i load = +10 m a v oh v ol v dd ?.1 0.1 v v output high voltage (i load =?ma) pa0-pa7, pb0-pb1, pc0-pc7, tcmp (ttl level) vttl, httl, sam v oh v dd ?.8 2.4 v v output low voltage (i load =+16ma) pa0-pa7, pc0-pc7, vttl, httl, sam, tcmp, scl, sdl (i load =+10ma) pb0-pb7 v ol 0.4 v input high voltage pa0-pa7, pb0-pb7, pc0-pc7, tcap, scl, sda, irq , reset , osc1 (ttl level) vsync, hsync, csync v ih 0.7xv dd 2.0 v dd v dd v v input low voltage pa0-pa7, pb0-pb5, pc0-pc7, tcap, scl, sda, irq , reset , osc1 (ttl level) vsync, hsync, csync v il v ss v ss 0.2xv dd 0.8 v v supply current: run wait stop 25 c 0 c to 70 c (standard) i dd 2.5 1.3 1.6 5.0 5.8 2.0 30 50 ma ma m a m a i/o ports high-z leakage current pa0-pa7, pb0-pb5, pc0-pc7, sda, scl, gpwm, rsa, rsb i il 10 m a input current irq , reset , osc1, vsync, hsync, tcap i in 1 m a capacitance ports (as input or output), reset , irq , osc1, osc2, tcap sda, scl, hsync, vsync, csync c out c in 12 8 pf pf low voltage reset threshold voltage v lvr 2.6 2.8 3.0 v notes: (1) all values shown re?ct average measurements. (2) typical values at midpoint of voltage range, 25 c only. (3) wait i dd : only timer system active. (4) run (operating) i dd , wait i dd : measured using external square wave clock source to osc1 (f osc =4.0mhz), all inputs 0.2 vdc from rail; no dc loads, less than 50pf on all outputs, c l =20pf on osc2. (5) wait, stop i dd : all ports con?ured as inputs, v il =0.2 vdc, v ih =v dd ?0.2 vdc. (6) stop i dd : measured with osc1 = v ss . (7) wait i dd is affected linearly by the osc2 capacitance. (8) irq should be pulled high at all times. tpg 110
mc68hc05bs8 motorola 13-3 electrical specifications 13 13.4 control timing table 13-2 control timing (v dd =5.0vdc 10%, v ss =0vdc, temperature range=0 to 70 c) characteristics symbol minimum maximum unit frequency of operation crystal option external clock option f osc dc 4.4 4.4 mhz mhz internal operating frequency (f osc /2) crystal external clock f op dc 2.2 2.2 mhz mhz processor cycle time t cyc 450 ns crystal oscillator start-up time (crystal option) t oxon 100 ms stop recovery start-up time (crystal option) t ilch 100 ms external reset pulse width t rl 1.5 t cyc power-on reset output width (4064 cycles) t porl 4064 t cyc watchdog reset output pulse width t dogl 1.5 t cyc watchdog time-out t dog 2 14 x 7 2 17 x 7 t cyc timer resolution (see note 1) input capture pulse width input capture pulse period t resl t icpw t icpp 4 125 (see note 2) 4 t cyc ns t cyc irq pulse width (edge-triggered) t ipw 125 ns irq pulse period t ipp (see note 2) t cyc pc0-pc5 interrupt pulse width low (edge-triggered) t kbipw 125 ns pc0-pc5 interrupt pulse period t kbipp (see note 2) t cyc osc1 pulse width t oh , t ol 90 ns eeprom byte erase time t ebyte ?0ms eeprom block erase time t block ?0ms eeprom bulk erase time t ebulk ?0ms eeprom program time t prog ?0ms notes: (1) the 2-bit timer prescaler is the limiting factor in determining timer resolution. (2) the minimum period t icppl , t ipp , or t kbipp should not be less than the number of cycles it takes to execute the interrupt service routine plus 19 t cyc . tpg 111
motorola 13-4 mc68hc05bs8 electrical specifications 13 13.5 pulse width modulator timing (v dd =5.0vdc 10%, v ss =0vdc, temperature range=0 to 70 c) parameter symbol minimum maximum unit gpwm frame period t gp 63 t cyc gpwm step size t s.gp 1t cyc rspwm frame period (cre=0, no pb7 reset) t rsp 127 t rclk rspwm step size t s.rsp 1t rclk rclk low pulse width t rckl 80 ns rclk high pulse width t rckh 80 ns pb7 counter reset low pulse width (cre=1) t pbrl 80 ns rclk to rs output delay t rckrd ?0ns pb7 to rs output delay (cre=0) t pbrd ?0ns note: t rclk is the rclk input signal period. figure 13-1 pwm timing scl t rckl t rckh t rclk t rckrd t pbrd t pbrl pb7 rsa or rsb tpg 112
mc68hc05bs8 motorola 13-5 electrical specifications 13 13.6 m-bus timing table 13-3 m-bus interface input signal timing (v dd =5.0vdc 10%, v ss =0vdc, temperature range=0 to 70 c) parameter symbol minimum maximum unit start condition hold time t hd.sta 2t cyc clock low period t low 4.7 t cyc clock high period t high 4t cyc data set-up time t su.dat 250 ns data hold time t hd.dat 0t cyc start condition set-up time (for repeated start condition only) t su.sta 2t cyc stop condition set-up time t su.sto 2t cyc table 13-4 m-bus interface output signal timing (v dd =5.0vdc 10%, v ss =0vdc, temperature range=0 to 70 c) parameter symbol minimum maximum unit start condition hold time t hd.sta 8t cyc clock low period t low 11 t cyc clock high period t high 11 t cyc sda/scl rise time (see note 1) t r ? m s sda/scl fall time (see note 1) t f 300 ns data set-up time t su.dat t low ?t cyc ?s data hold time t hd.dat 0t cyc start condition set-up time (for repeated start condition only) t su.sta 10 t cyc stop condition set-up time t su.sto 10 t cyc note: 1. with 200pf loading on the sda/scl pins figure 13-2 m-bus timing sda scl t high t hd.sta t low t su.dat t hd.dat t su.sta t su.sto t r t f tpg 113
motorola 13-6 mc68hc05bs8 electrical specifications 13 13.7 sync signal processor timing table 13-5 sync signal processor timing (v dd =5.0vdc 10%, v ss =0vdc, temperature range=0 to 70 c) parameter symbol minimum maximum unit vsync input sync pulse width t vi.sp 2 1023 t cyc vsync input period t vi 15360 48127 t cyc hsync input sync pulse width t hi.sp 1.5 16 t cyc hsync input period t hi 128 t cyc line per frame l frame 4095 line vttl output sync pulse width t vo.sp 6t vi.sp + 6 t ho free-running vttl output sync pulse width (sout clear) t fvo.sp 128 t cyc free-running vttl output period (sout clear) t fvo 31360 t cyc free-running httl output sync pulse width (sout clear) t fho.sp 8t cyc free-running httl output period (sout clear) t fho 35 t cyc inserted httl sync pulse (insrt cleared) t ihi.sp 4t cyc inserted httl period error (insrt cleared) t ihi.er ?t cyc sam sampling pulse width t sam 1t ho vsync to vttl delay (falling edge) t vvd ?0ns hsync to httl delay t hhd ?0ns hsync to vttl delay (rising edge) t hvd ?0ns csync to vttl delay t cvd ?0ns csync to httl delay t chd ?0ns note: t ho is the httl output signal period. tpg 114
mc68hc05bs8 motorola 14-1 mechanical specifications 14 14 mechanical specifications this section provides the mechanical dimensions for the 44-pin qfp package for the mc68hc05bs8. tpg 115
motorola 14-2 mc68hc05bs8 mechanical specifications 14 14.1 44-pin qfp package figure 14-1 44-pin qfp package (case no. 824a-01)

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mc68hc05bs8 motorola a-1 mc68hc705bs8 a a mc68hc705bs8 this appendix summarizes the differences between the mc68hc05bs8 and mc68hc705bs8. the same information can also be found in appropriate sections of the book. the mc68hc705bs8 is an eprom version of the mc68hc05bs8. the 10k-bytes of user rom in the mc68hc05bs8 are replaced by 10k-bytes of user eprom. a.1 features functionally equivalent to mc68hc05bs8 10k-bytes of user eprom eprom bootstrap mode replaces self-check mode on the mc68hc05bs8 a.2 memory map figure a-1 shows the memory map for the mc68hc705bs8. tpg 117
motorola a-2 mc68hc05bs8 mc68hc705bs8 a figure a-1 mc68hc705bs8 memory map bootstrap 512 bytes program port a data register $00 $0000 i/o 64 bytes bootstrap 16 bytes user vectors 16 bytes vectors port b data register $01 port c data register $02 not used $03 port a data direction register $04 port b data direction register $05 port c data direction register $06 eeprom register $07 core timer control and status register $08 core timer register $09 sync signal control and status register $0a vfreq register $0b $0c $0d $0e $0f $10 $11 timer control register $12 timer status register $13 input capture high register $14 input capture low register $15 output compare high register $16 output compare low register $17 counter high register $18 counter low register $19 alternate counter high register $1a alternate counter low register $1b eprom programming control register $1c option register $1d keyboard interrupt register $1e line frequency high register line frequency low register interrupt line count register sampling pulse register general purpose pulse width modulator register raster positioning pulse width modulator register not used (192) eeprom 512 bytes not used (4.25k) user eprom 10k-bytes $003f $0040 $00c0 $00ff $013f $0200 $03ff $1600 $17ff $3fdf $3fe0 $3fef $3ff0 $3fff $1800 keyboard $3ff0 m-bus $3ff2 ctimer $3ff4 timer $3ff6 vsync $3ff8 irq $3ffa swi $3ffc reset $3ffe not used $20 not used $38 $3f not used not used $3e not used $3d m-bus data register $3c m-bus status register $3b m-bus control register $3a m-bus frequency divider register $39 m-bus address register user ram 256 bytes stack 64 bytes $1f not used $0200 eeprom options register tpg 118
mc68hc05bs8 motorola a-3 mc68hc705bs8 a a.3 modes of operation the mc68hc705bs8 also has two modes of operation ?user mode and eprom bootstrap mode. table a-1 shows the conditions required to enter each mode on the rising edge of reset . a.3.1 user mode the normal operating mode of the mc68hc705bs8 is the user mode. the user mode will be entered if the reset line is brought low, and the irq pin is within its normal operational range (v ss to v dd ), the rising edge of the reset will cause the mcu to enter the user mode. warning: in the mc68hc705bs8, all vectors are fetched from eprom in user mode; therefore, the eprom must be programmed (via the bootstrap mode) before the device is powered up in user mode. a.3.2 bootstrap mode the bootstrap mode is provided in the mc68hc705bs8 as a mean of self-programming its eprom with minimal circuitry. it is entered on the rising edge of reset if irq pin is at 1.8v dd and pb6 is at logic one. reset must be held low for 4064 cycles after por (power-on reset). a.4 eprom programming the program control register (pcr) is provided for eprom programming. the function of the eprom depends on the device operating mode. table a-1 mc68hc705bs8 operating mode entry conditions reset irq pb6 mode v ss to v dd v ss to v dd user +9v rising edge* v dd bootstrap * minimum hold time should be 2 clock cycles, after that it can be used as a normal irq function pin. 5v 5v 9v tpg 119
motorola a-4 mc68hc05bs8 mc68hc705bs8 a a.4.1 program control register (pcr) elat - eprom latch control 1 (set) eprom address and data bus con?ured for programming (writes to eprom cause address data to be latched). eprom is in programming mode and cannot be read if elata is 1. this bit should not be set unless a programming voltage is applied to the v pp pin. 0 (clear) eprom address and data bus con?ured for normal reads. pgm - eprom program command 1 (set) programming power connected to the eprom array. if elat 1 1 then pgm = 0. 0 (clear) programming power disconnected from the eprom array. a.4.2 eprom programming sequence programming the eprom of the mc68hc705bs8 is as follows: 1) set the elat bit. 2) write the data to be programmed to the address to be programmed. 3) set the pgm bit. 4) delay for 1ms. 5) clear the pgm and the elat bits. the last action may be carried out in a single cpu write operation. it is important to remember that an external programming voltage must be applied to the v pp pin while programming, but should be equal to v dd during normal operation. example shows address $1900 is programmed with $00. clr pcr ;reset pcr ldx #$00 ;load index register with 00 bset 1,pcr ;set elat bit lda #$00 ;load data=00 in to a sta $1900,x ;latch data and address bset 0,pcr ;program jsr delay ;call delay subroutine for 1ms clr pcr ;reset pcr address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset $001c reserved elat pgm uuuu uu00 tpg 120
mc68hc05bs8 motorola a-5 mc68hc705bs8 a a.5 pin assignments a.6 electrical speci?ations a.6.1 maximum ratings figure a-2 pin assignments for 44-pin qfp package ratings symbol value unit latch-up current for irq i latch 120 ma irq /vpp reset osc2 12 13 15 16 17 18 19 20 21 22 14 33 32 30 29 28 27 26 25 24 23 31 pa0 pa1 pa3 pa4 pa5 pa6 pa7 pb0 pb1 pb2 pa2 vttl sda rclk rsa rsb gpwm tcmp tcap pc7 pc6 scl pc5 pc4 pc2 pc1 pc0 pb7 pb5 pb4 pb3 pc3 httl sam vsync hsync vss vdd osc1 csync 1 2 4 5 6 7 8 9 10 11 3 pb6 44 43 41 40 39 38 36 35 34 42 37 tpg 121
motorola a-6 mc68hc05bs8 mc68hc705bs8 a this page left blank intentionally tpg 122
1 2 3 4 5 6 7 8 9 10 11 12 13 14 a tpg 123 general description pin description input/output ports memory and registers resets and interrupts timers pulse width modulation m-bus serial interface sync signal processor cpu core and instruction set low power modes operating modes electrical specifications mechanical specifications mc68hc705bs8
1 2 3 4 5 6 7 8 9 10 11 12 13 14 a general description pin description input/output ports memory and registers resets and interrupts timers pulse width modulation m-bus serial interface sync signal processor cpu core and instruction set low power modes operating modes electrical specifications mechanical specifications mc68hc705bs8 tpg 124
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2 1 3 4 5 6 7 8 9 10 11 12 13 14 15 !motorola MC68HC05BS8D/h how to reach us: mfax: rmfax0@email.sps.mot.com ?touchtone (602) 244-6609 internet: http://design-net.com usa/europe/locations not listed: motorola literature distribution; p.o. box 20912; phoenix, arizona 85036. 1-800-441-2447 or 602-303-5454 japan: nippon motorola ltd.; tatsumi-spd-jldc, 6f seibu-butsuryu-center, 3-14-2 tatsumi koto-ku, tokyo 135, japan. 03-81-3521-8315 asia/pacific: motorola semiconductors h.k. ltd.; 8b tai ping industrial park, 51 ting kok road, tai po, n.t., hong kong. 852-26629298

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